公开(公告)号：JP2001202247A

公开(公告)日：2001-07-27

申请号：JP2000356504

申请日：2000-11-22

Applicant: ST MICROELECTRONICS SRL

Inventor： OCCHIPINTI LUIGI ,  DI COLA EUSEBIO ,  LAVORGNA MARIO

IPC: G06F7/544 ,  G05B13/02 ,  G06F9/44 ,  G06F15/78 ,  G06N3/00 ,  G06N3/04 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To obtain a new neuro-fuzzy integration architecture capable of realizing on-line self-training. SOLUTION: This architecture is provided with a fuzzy type microcontroller 11 exclusive for fuzzy rule calculation and integrated on a semiconductor together with a non-volatile memory 9 so as to be monolithic, and the same IC is provided with a microprocessor 5, a volatile memory unit 2, and an arbiter block 3 connected to a bus 4 connecting the fuzzy microcontroller 11 and the microprocessor 5 and the volatile memory unit 2. The arbiter block 3 controls access to the volatile memory unit 2 by the microcontroller 5 or the fuzzy microcontroller 11. Then, an additional fuzzy co-processor 6 for fuzzy logical arithmetic processing is connected between the fuzzy microcontroller 11 and the microprocessor 5.

公开(公告)号：JP2000112352A

公开(公告)日：2000-04-21

申请号：JP5845099

申请日：1999-03-05

Applicant: ST MICROELECTRONICS SRL

Inventor： OCCHIPINTI LUIGI ,  DI BERNARDO GIOVANNI ,  DI COLA EUSEBIO ,  CAPONETTO RICCARDO

IPC: G09C1/00 ,  H04L9/00 ,  H04L9/26 ,  H04L9/32

Abstract: PROBLEM TO BE SOLVED: To obtain a method for authentication and electronic signature of an enquiry type and a response type which have an improved security level by making a step generating a chaotic signal included in a step generating authentication and electronic signature signals. SOLUTION: A check terminal 2 checks identification data including a PIN (personal identification number) with respect to a card 1. Thereafter, the terminal 2 generates a signal or initial data X0 via a random value generating circuit 17 and moreover generates development time P. The terminal 2 transmits the initial data X0 and the signal of the development time to both of the card 1 and the chaotic generator of its own. The card 1 transfers the data and the signal to the chaotic generator 23 of its own and moreover calculates an authentication code RES' based on a secret key K' stored in a position 24 to transmit it to the terminal 2. The terminal 2 calculates a comparision code RES by using the secret key K stored in a position 29 to compare the RES with the authentication code RES' of the card 1.

公开(公告)号：JP2002258903A

公开(公告)日：2002-09-13

申请号：JP2001396005

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBISSO SALVATORE ,  CAPONETTO RICCARDO ,  DIAMANTE OLGA ,  PORTO DOMENICO ,  DI COLA EUSEBIO ,  FORTUNA LUIGI

IPC: G06N3/00 ,  G05B11/42 ,  G05B13/02

Abstract: PROBLEM TO BE SOLVED: To provide a circuit adapted for realizing a non-integral order dynamic system. SOLUTION: In this circuit for realizing a non-integral order dynamic system including a neural network(1-5) adapted for generating at least one output signal(OS) by receiving at least one input signal(IS), the input signal and output signal are related with each other in a non-integral order differential/integral relation based on the coefficients of the neutral network (1-5). A plurality of circuits (I, II) for realizing a non-integral order (PI D ) controller are connected to each other, and a signal is generated by either an integrating block (200) or a differentiating block (202) included in those circuits, and the signal is supplied to the integrating block (200) or the differentiating block (202) of the other circuit in this system.

公开(公告)号：JP2000138668A

公开(公告)日：2000-05-16

申请号：JP28864699

申请日：1999-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： ITALIA FRANSCECO ,  FORTUNA LUIGI ,  BERITELLI FRANCESCO ,  DI COLA EUSEBIO

IPC: H04L9/26 ,  H04L9/00 ,  H04L12/22 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To enhance a security level in an encipherment system based on a digital chaos model. SOLUTION: The processing is started from a couple of password codes or user keys, a discrete chaos model or map having a couple of the password codes or user keys is generated, a couple of the updated password codes or keys are dynamically generated for each processing step of a certain number in the chaos map, data to be transmitted in a transmission station are masked through logical combination with the dynamically updated keys at present, and a reception station eliminates the mask from the data by separating logically the digital data from the dynamically updated keys at present to restore the digital data in a clear state.

公开(公告)号：DE60211922D1

公开(公告)日：2006-07-06

申请号：DE60211922

申请日：2002-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： DI COLA EUSEBIO ,  TICLI LUCIO ,  MARTORANA ROSARIO ,  BARONE MARIO

IPC: F02D41/34 ,  F02D41/22 ,  F02D41/24

公开(公告)号：DE69828401D1

公开(公告)日：2005-02-03

申请号：DE69828401

申请日：1998-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ITALIA FRANCESCO ,  FORTUNA LUIGI ,  BERITELLI FRANCESCO ,  DI COLA EUSEBIO

IPC: H04L9/26 ,  H04L9/00 ,  H04L12/22

Abstract: A cryptation system for information transmitted through packet switching networks including masking the digital information data by combining them at the transmitting station with digital data of a certain code of cryptation before transmitting the so encrypted data through the network and performing an inverse decrypting processing at the receiving station using the same code of encrypting, comprises generating at a transmitting station and at a receiving station, starting from a given pair of password codes or user key, a certain discrete chaotic model or map of said pair of codes or key, producing dynamically updated pairs of values of codes or keys every certain number of processing steps of said chaotic map, masking the data to be transmitted by way of a logic combination with said current dynamically updated keys at the transmitting station, demasking the data at the receiving station by way of a logic decomposition of said digital data from said current dynamically updated key returning the digital data to a clear condition.

公开(公告)号：DE60211922T2

公开(公告)日：2007-02-01

申请号：DE60211922

申请日：2002-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： DI COLA EUSEBIO ,  TICLI LUCIO ,  MARTORANA ROSARIO ,  BARONE MARIO

IPC: F02D41/34 ,  F02D41/22 ,  F02D41/24

公开(公告)号：DE60018587D1

公开(公告)日：2005-04-14

申请号：DE60018587

申请日：2000-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBISSO SALVATORE ,  CAPONETTO RICCARDO ,  DIAMANTE OLGA ,  PORTO DOMENICO ,  DI COLA EUSEBIO ,  FORTUNA LUIGI

IPC: G06N3/00 ,  G05B11/42 ,  G05B13/02

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network (1 to 5) adapted to receive at least one input signal (IS) and to generate therefrom at least one output signal (OS). The input and output signals (IS, OS) are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network (1 to 5). A plurality (I, II) of such circuits, implementing respective non-integer order (PI D ) controllers can be interconnected in an arrangement wherein any of the integral (200) or differential (202) blocks included in one of those circuits generates a signal which is fed to any of the integral (200) or differential (204) blocks of another circuit in the system.

公开(公告)号：DE60322223D1

公开(公告)日：2008-08-28

申请号：DE60322223

申请日：2003-10-16

Applicant: ST MICROELECTRONICS SRL

Inventor： DI COLA EUSEBIO ,  RIVOLI FEDERICO ,  TICLI SALVATORE LUCIO ,  MARTORANA ROSARIO

IPC: G06N7/04

Abstract: In a process for performing fuzzy procedures in processing devices, of the type which provides for calculating a degree of activation ( alpha , alpha ') of a fuzzy proposition represented by input values (x), having a fuzzy set associated to a triangular or trapezoidal membership function (M,Ml,Mr,Mb,Me,T), said triangular or trapezoidal membership function (M,Ml,Mr,Mb,Me,T) being defined by a definition range (l0,r0;l1,r1) of said input values (x) and an abscissa of the maximum value (c0) assumed by said membership function (M,Ml,Mr,Mb,Me,T), there is provided storing solve values (l,c,r) corresponding to said range of definition (l0,r0;l1,r1) and to said abscissa of the maximum value (c0) and calculating said degree of activation ( alpha , alpha ') as a function of said solve values (l,c,r) stored, said operation of storing solve values (l,c,r) comprising storage of the values measured on the abscissa (c0,l0,r0,c0r0, l0c0;r1,l1,c0r1, l1c0) and further comprising storage of at least one value (y1,yr) measured on the ordinate and corresponding to said membership function (M,Ml,Mr,Mb,Me,T), instead of at least one of said values measured on the abscissa (c0r1,l1c0), if at least one of said values (c0r1,l1c0) measured on the abscissa assumes an absolute value greater than a maximum representable value (n).

公开(公告)号：DE69832038D1

公开(公告)日：2005-12-01

申请号：DE69832038

申请日：1998-03-06

Applicant: ST MICROELECTRONICS SRL

Inventor： OCCHIPINTI LUIGI ,  DI BERNARDO GIOVANNI ,  DI COLA EUSEBIO ,  CAPONETTO RICCARDO

IPC: G09C1/00 ,  H04L9/00 ,  H04L9/26 ,  H04L9/32 ,  G01N30/00

Abstract: The method for authentication and electronic signature is of the private-key, challenge and response type between a user requesting an authorisation (for a specific transaction, or for access to particular resources), via, for example, a smart card (1) and a controller -check terminal (2)-supplying the authorisation. To increase security of the authorisation or authentication operations, the smart card (1) comprises a chaotic generator (23) generating user's acknowledgement code, which is compared with a comparison code generated by the check terminal (2) using a chaotic generator (30) which is the same.