公开(公告)号：JPH10313067A

公开(公告)日：1998-11-24

申请号：JP34684397

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SRL

Inventor： SONEGO PATRIZIA ,  BACCHETTA MAURIZIO

IPC: H01L23/14 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain an intermediate dielectric layer planarized to a high degree for optimizing a plurality of electronic devices integrated on a semiconductor substrate by a method wherein a dielectric layer is formed of a liquid supply source by adhering on a first insulative dielectric layer, then, the intermediate dielectric layer is formed of a siloxane SOG layer, which is formed by solidifying the dielectric layer by a polymerization process and has high planarization characteristics. SOLUTION: Electronic devices, which are respectively provided with gate regions 2, are integrated on a semiconductor substrate 1 and those devices are completely covered with a first insulative dielectric layer 3, which is formed by adhering at a low temperature, is not doped and consists of a silicon oxide film. A dielectric layer consisting of a siloxane SOG layer is made to adhere on the first layer 3 from a liquid phase until voids 4 among the regions 2 are filled utilizing a spining technique and the SOG material layer is solidified to a second intermediate dielectric layer 6 flattened to a high degree by a thermal treatment for bringing into the state of higher density. Moreover, a rapid thermal annealing process and the like are executed, an organic material existing in the layer 6 is flattened out and the layer 6 is brought into the state of higher density and is converted to a silicon oxide layer.

公开(公告)号：JPH07307339A

公开(公告)日：1995-11-21

申请号：JP8235395

申请日：1995-04-07

Applicant: ST MICROELECTRONICS SRL

Inventor： LOSAVIO ALDO ,  BACCHETTA MAURIZIO

IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an insulating film which has a highly flat surface without needing heat treatment at high temperature, by forming a barrier layer of an undoped oxide substance on a semiconductor substrate, and stacking an oxide layer in higher phosphorus concentration than boron concentration, and further, heat-treating it after formation of an oxide layer including boron. CONSTITUTION: The first undoped oxide layer (barrier layer) 12 is stacked all over the surface of an integrated circuit by CVD technique. Thereon, the second oxide layer 13 is stacked, using CVD technique, and at this time, the concentration of phosphor for doping is made higher than the concentration of boron. Furthermore, thereon the third oxide layer 14 is stacked by CVD technique, and the concentration of phosphor for doping within this layer is made over the concentration of phosphor, and the fusing-point temperature is selected to drop to a desired value. Lastly, heat treatment is performed to reflow the third oxide layer 14, whereby the surface of the integrated circuit is flattened. As a result, a highly flat insulating film can be obtained without needing heat treatment at high temperature.

公开(公告)号：JPH07142730A

公开(公告)日：1995-06-02

申请号：JP13962094

申请日：1994-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BACCHETTA MAURIZIO ,  BACCI LAURA ,  ZANOTTI LUCA

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/31 ,  H01L23/532

Abstract: PURPOSE: To improve the adhesive strength of an interface between layers of insulating materials during the manufacture of an integrated circuit which has a multilayered structure. CONSTITUTION: For a method of improving the adhesion state of an interface between the insulating material layers during the manufacture of a semiconductor device, a 1st insulating layer 1 is formed of an insulating material on a circuit structure 7 which is formed on a substrate 6 of a semiconductor substrate, then a 2nd insulating layer 3 of an insulating material is out over the 1st insulating layer 1, and a thin oxide layer 2 is formed in an adhered state between the 1st and 2nd insulating layers 1 and 3. This inserted oxide layer 2 functions as an adhesion layer between the two superimposed insulating layers 1 and 3.

公开(公告)号：DE69417211T2

公开(公告)日：1999-07-08

申请号：DE69417211

申请日：1994-04-12

Applicant: ST MICROELECTRONICS SRL

Inventor： LOSAVIO ALDO ,  BACCHETTA MAURIZIO

IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792

Abstract: A planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices, comprises the steps of: forming a first layer (12) of undoped oxide acting as a barrier layer over a semiconductor substrate (3) wherein integrated devices (M,MC1,MC2) have been previously obtained; forming a second layer (13) of oxide containing phosphor over the first undoped oxide; forming a third layer (14) of oxide containing phosphor and boron over the second oxide layer, the concentration of phosphor being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer (14), to obtain a planar surface.

公开(公告)号：DE69333722T2

公开(公告)日：2005-12-08

申请号：DE69333722

申请日：1993-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BACCHETTA MAURIZIO ,  BACCI LAURA ,  ZANOTTI LUCA

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2) is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

公开(公告)号：DE69432352D1

公开(公告)日：2003-04-30

申请号：DE69432352

申请日：1994-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： BACCHETTA MAURIZIO ,  ZANOTTI LUCA ,  QUEIROLO GIUSEPPE

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/532

公开(公告)号：DE69417211D1

公开(公告)日：1999-04-22

申请号：DE69417211

申请日：1994-04-12

Applicant: ST MICROELECTRONICS SRL

Inventor： LOSAVIO ALDO ,  BACCHETTA MAURIZIO

IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792

Abstract: A planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices, comprises the steps of: forming a first layer (12) of undoped oxide acting as a barrier layer over a semiconductor substrate (3) wherein integrated devices (M,MC1,MC2) have been previously obtained; forming a second layer (13) of oxide containing phosphor over the first undoped oxide; forming a third layer (14) of oxide containing phosphor and boron over the second oxide layer, the concentration of phosphor being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer (14), to obtain a planar surface.

公开(公告)号：DE69333722D1

公开(公告)日：2005-01-20

申请号：DE69333722

申请日：1993-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BACCHETTA MAURIZIO ,  BACCI LAURA ,  ZANOTTI LUCA

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2) is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

公开(公告)号：DE69432352T2

公开(公告)日：2004-03-04

申请号：DE69432352

申请日：1994-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： BACCHETTA MAURIZIO ,  ZANOTTI LUCA ,  QUEIROLO GIUSEPPE

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/532