公开(公告)号：JPH11214529A

公开(公告)日：1999-08-06

申请号：JP30387798

申请日：1998-10-26

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  BOLOGNESI DAVIDE ,  MARI ANGELO

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make it possible to integrate a plurality of MOS devices of different voltage thresholds in one and the same substrate, by a method wherein when forming a plurality of channel regions for the MOS devices, impurities are selectively doped into a geometrical pattern with a gate electrode as a mask. SOLUTION: After a gate oxide film 3 and a polycrystalline silicon layer 4 are formed, these layers 3, 4 are selectively removed to form square openings for a transistor 1' and stripe openings for a transistor 1" to form a gate electrode 5, 5' for the transistor 1', 1". Then, with the gate electrode 5, 5' as a mask, P-type impurities are selectively doped into a drain layer 2 to form the main body region 7 of the transistor 1', 1". The main body region 7 has a square or stripe shape and is extended under the gate electrode 5, 5' to form a channel region of the transistor. Again, N-type impurities are selectively doped into the main body region 7 with the gate electrode 5, 5' as a mask to form a source region.

公开(公告)号：DE69734982D1

公开(公告)日：2006-02-02

申请号：DE69734982

申请日：1997-10-24

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  BOLOGNESI DAVIDE ,  MAGRI ANGELO

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

公开(公告)号：DE69534488D1

公开(公告)日：2006-02-09

申请号：DE69534488

申请日：1995-07-31

Applicant: ST MICROELECTRONICS SRL

Inventor： LEONARDI SALVATORE ,  BOLOGNESI DAVIDE

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/08