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    HIGH DENSITY MOS TECHNOLOGY POWER DEVICE STRUCTURE
    1.
    发明专利
    HIGH DENSITY MOS TECHNOLOGY POWER DEVICE STRUCTURE 失效

    公开(公告)号：JP2000058829A

    公开(公告)日：2000-02-25

    申请号：JP13955599

    申请日：1999-05-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide the structure of a high density MOS technology power device provided with a first conductivity-type base area formed in a second conductivity-type semiconductor layer. SOLUTION: A base area has at least pairs of substantially linear and substantially parallel base stripes 32. The respective base stripes 32 are connected to the adjacent base stripes 32 at end parts by a junction area. Thus, at least the pairs of base stripes 32 and the junction area can form continuous meandered base areas 31A-31D.

    METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE 审中-公开
    制造半导体功率器件的方法

    公开(公告)号：WO2007006764A3

    公开(公告)日：2007-03-15

    申请号：PCT/EP2006064035

    申请日：2006-07-07

    Applicant: ST MICROELECTRONICS SRL ,  ARENA GIUSEPPE ,  DONATO CATERINA ,  CAMALLERI CATENO MARCO ,  MAGRI ANGELO

    Inventor： ARENA GIUSEPPE ,  DONATO CATERINA ,  CAMALLERI CATENO MARCO ,  MAGRI ANGELO

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/511 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

    Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积厚度小于第一介电材料层（9）的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在所述半导体本体（2）的所述栅极区域（14）的侧面和与所述栅极区域（14）绝缘的状态下，在所述半导体本体（2）中形成所述主体区域（7）和源极区域 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES
    3.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 审中-公开
    用于制造集成在半导体衬底和相应器件中的电子器件的方法

    公开(公告)号：WO2007006504A2

    公开(公告)日：2007-01-18

    申请号：PCT/EP2006006672

    申请日：2006-07-07

    Applicant: ST MICROELECTRONICS SRL ,  FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    Inventor： FRISINA FERRUCCIO ,  SAGGIO MARIO GIUSEPPE ,  MAGRI ANGELO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

    CPC classification number: H01L29/1095 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7802 ,  H01L29/7835

    Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1, 1a; 10, 11) with wide band gap comprising the steps of: forming a screening structure (3a, 20) on said semiconductor substrate (1, 1a; 10, 11) comprising at least a dielectric layer (2, 20) which leaves a plurality of areas of said semiconductor substrate (1, 1a; 10, 11) exposed, carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a first implanted region (4, 40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a second implanted region (6, 6c; 60, 61) inside said at least a first implanted region (4, 40), carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4, 40; 6, 60).

    Abstract translation: 在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法包括以下步骤：在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20），包括： 至少一个留下所述半导体衬底（1,1a; 10,11）的多个区域的介电层（2,20），所述多个区域暴露在所述半导体衬底（1）中至少进行第一类型的掺杂剂的离子注入 ，1a; 10,11）以形成至少第一注入区域（40,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型的掺杂剂的离子注入以形成 在所述至少第一注入区域（4,40）内部的至少一个第二注入区域（6,6c; 60,61）中，执行所述第一类型和第二类型的掺杂剂的激活热过程，其具有适合于完成 所述至少第一和第二植入区域（4,40; 6,60）的形成。

    7.
    发明专利
    未知

    公开(公告)号：DE69533134D1

    公开(公告)日：2004-07-15

    申请号：DE69533134

    申请日：1995-10-30

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.

    8.
    发明专利
    未知

    公开(公告)号：DE602004011195T2

    公开(公告)日：2009-01-08

    申请号：DE602004011195

    申请日：2004-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERRARA MAURIZIO MARIA ,  MAGRI ANGELO ,  MINOTTI AGATINO

    IPC: H01L23/31 ,  H01L23/495 ,  H01L23/52

    Abstract: A vertical conduction power electronic device package (1) and corresponding assembly method comprising at least a metal frame (2) suitable to house at least a plate or first semiconductor die (16,35) having at least a first (17) and a second conduction terminal (18) on respective opposed sides of the first die (16,35). The first conduction terminal (17) being in contact with said metal frame (2) and comprising at least an intermediate frame (23,24) arranged in contact with said second conduction terminal (18).

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