公开(公告)号：JPH08213614A

公开(公告)日：1996-08-20

申请号：JP19759695

申请日：1995-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a parasitic resistance value and inductance of wire and pin by separating units comprising a plurality of function units with such a region of a semiconductor layer as no function unit is formed. SOLUTION: A semiconductor material layer 5 is selectively coated with an insulated gate layer 11 extending on a first doped region 7, and the gate layer 11 is made to contact gate metal meshes 101 and 102 connected to at least one gate metal pad, while surrounding a source metal plate 100. By connecting the gate metal pad to each pin P8 of a package with each bonding wire W8, all MOSFET units among all the MOSEFT units are connected in parallel. Thus, the maximum current capacity of the power device can be re- established, while each source electrode pin can be electrically speared according to individual purposes, resulting in significantly improved freedom in design.

公开(公告)号：JPH0817848A

公开(公告)日：1996-01-19

申请号：JP15598295

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

Abstract: PURPOSE: To ignore the base series resistance of a parasitic perpendicular bipolar transistor by adjusting an ion implantation energy so that the peak of the dopant concentration of a heavily doped part of a body region is located on the lower side of a source region than the surface of a semiconductor layer. CONSTITUTION: With an insulation gate layer 10 on the surface of a semiconductor layer 3 as a mask, a first impurity is ion-implanted with an energy in a specific thickness from the surface of the semiconductor layer 3 and is thermally diffused, thus forming a body region 2 consisting of a first greatly doped part 5 that is nearly aligned to both edges of the insulation layer 10 and a horizontal diffusion part 6 at the lower side of the insulation layer 10. The second impurity is ion-implanted selectively into the body region 2 in a pair, thus forming an annular source 7 that is aligned to both edges of the insulation layer 10, thus forming the greatly doped part 5 of the first impurity so that it is located at the lower side of the annular source region 7 and ignoring the base series resistance of a parasitic perpendicular bipolar transistor.

公开(公告)号：JP2000138232A

公开(公告)日：2000-05-16

申请号：JP28383899

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: G11C29/14 ,  G11C29/50 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device which does not raise problems related to threshold voltage, even if a normal insulating material is used for forming an insulating spacer and will not raise strain causing dislocations or cracks in silicon, even if another material such as silicon nitride is used. SOLUTION: This power semiconductor device has a second insulating material region 10 positioned at a side part of a polysilicon layer 5 and a first insulating material region 6, and at the upper side of a region 14 positioned near the opening at the upper side of an insulation layer body region 2 of a gate oxide layer 4, an oxide region 9 formed between a polysilicon region 5 and the second insulating material region 10, and an oxide spacer 8 formed in the upper side of a second material region.

公开(公告)号：JPH0864811A

公开(公告)日：1996-03-08

申请号：JP19326495

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

公开(公告)号：JP2003152160A

公开(公告)日：2003-05-23

申请号：JP2002316673

申请日：2002-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGLI ANGELO

IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

Abstract: PROBLEM TO BE SOLVED: To improve electric connection between an electronic power device and a package and avoid the formation of an uncontrollable chemical composition area. SOLUTION: The electronic power device (1) having an improved structure is manufactured by employing MOS technique so as to have at least one gate finger area (3) and related source areas (4) positioned at both sides of the area (3). The electronic power device is provided with at least first level metallic layers (3', 4') arranged so as to be contacted individually with the gate finger area and the source areas, and a passivation layer (5) for protection which is arranged so as to cover the gate finger area. A wetting metallic layer (7) is advantageous to be built up on the passivation layer and the first level metallic layer (4') for covering the source area. According to this method, an additional wetting metallic layer functions as a second level metallic layer.

公开(公告)号：JP2000058829A

公开(公告)日：2000-02-25

申请号：JP13955599

申请日：1999-05-20

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a high density MOS technology power device provided with a first conductivity-type base area formed in a second conductivity-type semiconductor layer. SOLUTION: A base area has at least pairs of substantially linear and substantially parallel base stripes 32. The respective base stripes 32 are connected to the adjacent base stripes 32 at end parts by a junction area. Thus, at least the pairs of base stripes 32 and the junction area can form continuous meandered base areas 31A-31D.

公开(公告)号：JP2000183348A

公开(公告)日：2000-06-30

申请号：JP34999899

申请日：1999-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS gate power device with low output resistance. SOLUTION: A MOS gate power device is provided with plural element function units. The element function units are provided with first conductivity- type main body regions 3 formed in second conductivity-type semiconductor material layers 2, 21, 22 and 23. Plural first conductivity-type impurity addition regions 20, 201 and 202 are formed in the semiconductor material layers 2, 21, 22 and 23, and the impurity addition regions 20, 201 and 202 are arranged below the respective main body regions 3 and are detached from the adjacent impurity addition regions by the semiconductor material layers 2, 21, 22 and 23.

公开(公告)号：JP2000164841A

公开(公告)日：2000-06-16

申请号：JP28993099

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： POLMAN ALBERT ,  HAMELIN NICHOLAS ,  KIK PETER ,  COFFA SALVATORE ,  FRISINA FERRUCCIO ,  SAGGIO MARIO

IPC: H01L31/108 ,  G01J1/02 ,  G02B6/12 ,  H01L27/14 ,  H01L31/0352 ,  H01L31/103

Abstract: PROBLEM TO BE SOLVED: To obtain an infrared detector device, exhibiting a high efficiency of transfer from infrared radiation to electrical currents by a semiconductor material. SOLUTION: An infrared detector device 1 is provided with P-N junctions 9 and 10, comprised of a first semiconductor material region 9 doped with rare-earth ions and a second semiconductor material region 10 of the oppositely doped type P. The detector device extends on a substrate 2, including a reflection layer 4 and is provided with a wave guide path 8 formed by protrusions whose range in horizontal direction is demarcated by an oxide a region for protection and containment. At least a part of the wave guide path 8 is formed of a P-N junction and has an end to which light to be detected is supplied. The detector device has electrodes 18 and 13, placed on the side and top of the wave guide path 8 and enables efficient collection of charge carriers produced by optical transfer.

公开(公告)号：JPH11214529A

公开(公告)日：1999-08-06

申请号：JP30387798

申请日：1998-10-26

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  BOLOGNESI DAVIDE ,  MARI ANGELO

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make it possible to integrate a plurality of MOS devices of different voltage thresholds in one and the same substrate, by a method wherein when forming a plurality of channel regions for the MOS devices, impurities are selectively doped into a geometrical pattern with a gate electrode as a mask. SOLUTION: After a gate oxide film 3 and a polycrystalline silicon layer 4 are formed, these layers 3, 4 are selectively removed to form square openings for a transistor 1' and stripe openings for a transistor 1" to form a gate electrode 5, 5' for the transistor 1', 1". Then, with the gate electrode 5, 5' as a mask, P-type impurities are selectively doped into a drain layer 2 to form the main body region 7 of the transistor 1', 1". The main body region 7 has a square or stripe shape and is extended under the gate electrode 5, 5' to form a channel region of the transistor. Again, N-type impurities are selectively doped into the main body region 7 with the gate electrode 5, 5' as a mask to form a source region.

公开(公告)号：JPH0897168A

公开(公告)日：1996-04-12

申请号：JP16869395

申请日：1995-07-04

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of highly integrated MOS power device. SOLUTION: Insulating gate layers 8 and insulating layers 11 are formed on a semiconductor layer 2, next to a plurality of slender windows having long edges 17 and short edges sectioning respectively exposed surface fine strips 16 are formed by selectively removing layers 8 and 11. Then the slender windows are implanted with a first dopant vertically thereto and perpendicularly to the layer 2 so as to be symmetrically tilted at the surface of the layer 2 making an angle. These angles depending upon the gross thickness of the layers 8 and 11 for preventing the first dopant from being implanted into the central fine strips of the fine strips 16 to form the pairs of source regions 6 extending along the edges 17 of respective windows, also separated by the central fine strips further symmetrically tilted making another angle to be implanted with a second dopant to form respective regions with two channel regions 5, extending to the under side of the long edges of respective windows finally implanted with a third dopant to form the regions aligned with the edges 17 of the windows using the layers 11 as masks.