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    MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE
    1.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE 失效

    公开(公告)号：JPH1174490A

    公开(公告)日：1999-03-16

    申请号：JP17749698

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  PIO FEDERICO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a simple manufacturing method of a semiconductor memory device having storage memory cells and shielded memory cells shielded so as to prevent their stored informations from being read out by external systems. SOLUTION: In the same chip made of semiconductor materials, there are formed at least one first memory cells each of which has a MOS transistor with overlapping first and second gates with each other formed respectively in first and second conductive material layers 12, 17 and at least one second memory cells each of which is so shielded by a shield material layer 32 that no external system can access to its storing information. This second memory cell comprises a MOS transistor having a floating gate formed of the first conductive material layer 12 simultaneously with the foregoing first gate electrode of the foregoing first memory cell, and the shield material layer 32 is formed of the second conductive material layer 17.

    4.
    发明专利
    未知

    公开(公告)号：ITMI982082A1

    公开(公告)日：2000-03-29

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

    6.
    发明专利
    未知

    公开(公告)号：IT1303282B1

    公开(公告)日：2000-11-06

    申请号：ITMI982334

    申请日：1998-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

    Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

    7.
    发明专利
    未知

    公开(公告)号：IT1302282B1

    公开(公告)日：2000-09-05

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

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