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    1.
    发明专利
    未知

    公开(公告)号：ITTO980516A1

    公开(公告)日：1999-12-13

    申请号：ITTO980516

    申请日：1998-06-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZATELLI NICOLA ,  CREMONESI CARLO ,  CLEMENTI CESARE ,  PIO FEDERICO

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

    Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

    2.
    发明专利
    未知

    公开(公告)号：IT1303282B1

    公开(公告)日：2000-11-06

    申请号：ITMI982334

    申请日：1998-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

    Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

    3.
    发明专利
    未知

    公开(公告)号：IT1302282B1

    公开(公告)日：2000-09-05

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

    6.
    发明专利
    未知

    公开(公告)号：ITMI981449A1

    公开(公告)日：1999-12-25

    申请号：ITMI981449

    申请日：1998-06-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CREMONESI CARLO ,  ZATELLI NICOLA ,  PIO FEDERICO

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

    7.
    发明专利
    未知

    公开(公告)号：DE69841040D1

    公开(公告)日：2009-09-17

    申请号：DE69841040

    申请日：1998-12-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  VAJANA BRUNO ,  DALLA LIBERA GIOVANNA ,  CREMONESI CARLO ,  GALBIATI NADIA

    IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105

    Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

    10.
    发明专利
    未知

    公开(公告)号：ITMI982082A1

    公开(公告)日：2000-03-29

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

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