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    METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR POWER DEVICE 审中-公开
    制造半导体功率器件的方法

    公开(公告)号：WO2007006764A3

    公开(公告)日：2007-03-15

    申请号：PCT/EP2006064035

    申请日：2006-07-07

    Applicant: ST MICROELECTRONICS SRL ,  ARENA GIUSEPPE ,  DONATO CATERINA ,  CAMALLERI CATENO MARCO ,  MAGRI ANGELO

    Inventor： ARENA GIUSEPPE ,  DONATO CATERINA ,  CAMALLERI CATENO MARCO ,  MAGRI ANGELO

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/511 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

    Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积厚度小于第一介电材料层（9）的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在所述半导体本体（2）的所述栅极区域（14）的侧面和与所述栅极区域（14）绝缘的状态下，在所述半导体本体（2）中形成所述主体区域（7）和源极区域 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

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