公开(公告)号：DE602005025845D1

公开(公告)日：2011-02-24

申请号：DE602005025845

申请日：2005-11-18

Applicant: ST MICROELECTRONICS SRL

Inventor： ARENA GIUSEPPE ,  FERLA GIUSEPPE ,  CAMALLERI MARCO

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423

公开(公告)号：DE69941456D1

公开(公告)日：2009-11-05

申请号：DE69941456

申请日：1999-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： D ARRIGO GIUSEPPE ,  SPINELLA CORRADO ,  COFFA SALVATORE ,  ARENA GIUSEPPE ,  CAMALLERI MARCO

IPC: H01L21/762 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/321

Abstract: This invention relates to a method of fabricating a SOI (Silicon-On-Insulator) wafer suitable to manufacture electronic semiconductor devices and including a substrate of monocrystalline silicon with a top surface, and a doped buried region in the substrate. The method comprises at least one step of forming trench-like openings extended from the substrate surface down to the buried region, and comprises: a selective etching step carried out through said openings to change said buried region of monocrystalline silicon into porous silicon; a subsequent step of oxidising the buried region that has been changed into porous silicon, to obtain an insulating portion of said SOI wafer.

公开(公告)号：ITMI20042243A1

公开(公告)日：2005-02-19

申请号：ITMI20042243

申请日：2004-11-19

Applicant: ST MICROELECTRONICS SRL

Inventor： ARENA GIUSEPPE ,  CAMALLERI MARCO ,  FERLA GIUSEPPE