公开(公告)号：JP2001168303A

公开(公告)日：2001-06-22

申请号：JP24214498

申请日：1998-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: G11C16/04 ,  G11C8/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic memory device which is integrated on a semiconductor containing a virtual ground cell matrix. SOLUTION: A matrix is formed on a semiconductor substrate 10 as it is provided with continuous bit lines 7 which extend as discrete parallel stripes traversing a substrate 10. The matrix contains a circuit part C' for selective transistors 20, and a decoder equipped with a P-channel and an N-channel MOS transistor and an address circuits A and B are built in a memory device. A process in which an N well 11 where the P-channel transistor is housed is formed on a part A of the substrate, and another process in which the active regions of all transistors are specified by a screen mask 33 and an isolation layer 13 is grown through the intermediary of an opening provided to the mask 33, are at least provided. The active region specifying mask 33 is not opened on the matrix region C" of the memory cell.

公开(公告)号：DE69732293D1

公开(公告)日：2005-02-24

申请号：DE69732293

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIO VALERIO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

公开(公告)号：DE69739045D1

公开(公告)日：2008-11-27

申请号：DE69739045

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors. The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.