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    METHOD FOR MANUFACTURING MEMORY CELL
    1.
    发明专利
    METHOD FOR MANUFACTURING MEMORY CELL 审中-公开

    公开(公告)号：JP2003163294A

    公开(公告)日：2003-06-06

    申请号：JP2002294069

    申请日：2002-10-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPRARA PAOLO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO

    IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To simplify the step of manufacturing a double charge storage location memory cell. SOLUTION: A dielectric stack 120 is disposed over the entire upper side surface of a structure. A contact opening 121 is formed in the dielectric layer 120 lowered to the surface of a bit line diffused part 115 of the specified region at the outside of the memory cell sub-array. Metal bit lines 123A, 123B are specified to cross a word line 119 on the bit line diffused part 115 so as to bring into contact with the position corresponding to the specified region by a normal contact forming technique and a metallization technique. The metal bit line restricts the voltage drop along the bit line diffused part 115. COPYRIGHT: (C)2003,JPO

    ELECTRONIC VIRTUAL GROUND MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明专利
    ELECTRONIC VIRTUAL GROUND MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效

    公开(公告)号：JP2001168303A

    公开(公告)日：2001-06-22

    申请号：JP24214498

    申请日：1998-08-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

    IPC: G11C16/04 ,  G11C8/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic memory device which is integrated on a semiconductor containing a virtual ground cell matrix. SOLUTION: A matrix is formed on a semiconductor substrate 10 as it is provided with continuous bit lines 7 which extend as discrete parallel stripes traversing a substrate 10. The matrix contains a circuit part C' for selective transistors 20, and a decoder equipped with a P-channel and an N-channel MOS transistor and an address circuits A and B are built in a memory device. A process in which an N well 11 where the P-channel transistor is housed is formed on a part A of the substrate, and another process in which the active regions of all transistors are specified by a screen mask 33 and an isolation layer 13 is grown through the intermediary of an opening provided to the mask 33, are at least provided. The active region specifying mask 33 is not opened on the matrix region C" of the memory cell.

    4.
    发明专利
    未知

    公开(公告)号：DE69739045D1

    公开(公告)日：2008-11-27

    申请号：DE69739045

    申请日：1997-08-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

    IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

    Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors. The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.

    5.
    发明专利
    未知

    公开(公告)号：DE69926733D1

    公开(公告)日：2005-09-22

    申请号：DE69926733

    申请日：1999-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522

    Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps: forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another; forming a fill layer (4) in the gaps between said regions (3) ; planarizing said fill layer (4) to expose said regions (3) ; removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3); forming an insulating layer (6) in said holes (5); selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ; depositing at least one conductive layer (8) all over the exposed surface; photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).

    10.
    发明专利
    未知

    公开(公告)号：DE69636738D1

    公开(公告)日：2007-01-11

    申请号：DE69636738

    申请日：1996-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMERLENGHI EMILIO ,  CAPRARA PAOLO ,  FONTANA GABRIELLA

    IPC: H01L21/28 ,  H01L27/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: The present invention relates to a process for creation of contacts (25) in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure comprising memory cell matrices in which the bit lines are parallel unbroken diffusion strips (12) extending along a column of the matrix with the contacts (25) being provided through associated contact apertures (24) defined through a dielectric layer (21) deposited over a contact region defined on a semiconductor substrate (11) at one end of the bit lines (12). The process calls for a step of implantation and following diffusion of contact areas (22) provided in the substrate (11) at opposite sides of each bit line (12) to be contacted to widen the area designed to receive the contacts (25).

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