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    MANUFACTURING PROCESS OF SEMICONDUCTOR NONVOLATILE MEMORY DEVICE BY SHALLOW-GROOVE INSULATION
    1.
    发明专利
    MANUFACTURING PROCESS OF SEMICONDUCTOR NONVOLATILE MEMORY DEVICE BY SHALLOW-GROOVE INSULATION 失效

    公开(公告)号：JP2000188345A

    公开(公告)日：2000-07-04

    申请号：JP18299099

    申请日：1999-06-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLPANI PAOLO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To guarantee the electrical continuity of the common power supply area of a memory device by etching the area with an active range line not covered with a first polysilicon line so as to reduce the level difference along a common power supply line between the area of the active range line and that of a field oxide line. SOLUTION: In a fifth etching sub-step, the area of an active range line 3 not covered with a first polysilicon line 7' is etched simultaneously with the etching of the line 7' so as to reduce the level difference along a common power supply line between the area of the active range line 3 and that of a field oxide line 5 and, accordingly, to guarantee the electrical continuity of the common power supply area of a memory device. In other words, the aspect ratio between the active range 3 and insulating area 5 can be reduced in the defining step of a word line 6 in order to guarantee the electrical continuity between a high- silicon area and a low-silicon area along the common power supply line.

    Verfahren zur Reduzierung von thermomechanischer Belastung in Halbleitervorrichtungen und entsprechende Vorrichtung
    5.
    发明专利
    Verfahren zur Reduzierung von thermomechanischer Belastung in Halbleitervorrichtungen und entsprechende Vorrichtung 未知

    公开(公告)号：DE102016118653A1

    公开(公告)日：2017-08-03

    申请号：DE102016118653

    申请日：2016-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLPANI PAOLO ,  MILANI ANTONELLA ,  GUARINO LUCREZIA ,  PALEARI ANDREA

    IPC: H01L21/768 ,  H01L23/50

    Abstract: In einer Ausführungsform weist eine Halbleitervorrichtung eine oder mehrere Metallisierungen (10), beispielsweise Cu-RDL-Metallisierungen, auf, die auf einer Passivierungsschicht (12) über einer dielektrischen Schicht (22) vorgesehen sind. Ein Durchgangsloch (16) durch die Passivierungsschicht (12) und die elektrische Schicht (22) ist in der Nachbarschaft der Ecken (10a, 10b) der Metallisierung vorgesehen. Dieses Durchgangsloch kann ein „Dummy”-Durchgangsloch ohne elektrische Verbindungen zu einer aktiven Vorrichtung sein und kann mit einem Abstand zwischen circa 1 Mikrometer (10–6 m.) und circa 10 Mikrometer (10–5 m.) von jeder der zusammenlaufenden Seiten (10b) vorgesehen sein und auf eine unterliegende Mittelschicht (24) auftreffen.

    6.
    发明专利
    未知

    公开(公告)号：DE69802509D1

    公开(公告)日：2001-12-20

    申请号：DE69802509

    申请日：1998-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLPANI PAOLO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: Process for the fabrication of a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, comprising a first step of forming active area's parallel lines (3) delimited by field oxide lines (5) by means of a Shallow Trench Isolation process, a second step of forming matrix rows (6) which extend transversally to the active area lines (3), a third step of forming common source lines alternated between pairs of the matrix rows (6). The second step comprises a first sub-step of forming first lines (7') in a first polysilicon layer, along the active area lines (3), a second sub-step of forming an intermediate dielectric layer (9), a third sub-step of forming second lines (6) in a second polysilicon layer for defining the matrix rows (6), a fourth sub-step of defining the intermediate dielectric layer (9), a fifth sub-step of etching the first polysilicon lines (7'). The first polysilicon lines (7') have interruptions in regions of the active area lines (3) corresponding to the future common source lines of the matrix, so that, during the fifth etching sub-step, simultaneously with the first polysilicon lines (7') etching, the regions of the active area lines (3) not covered with the first polysilicon lines (7') are etched in order to reduce the difference of level along the common source lines between the regions of the active area lines (3) and the regions of the field oxide lines (5) and consequently to guarantee the electrical continuity of the common source regions of the memory device.

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