公开(公告)号：FR2908919B1

公开(公告)日：2014-03-07

申请号：FR0759104

申请日：2007-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONIO ,  MICCICHE MARIO ,  LO GIUDICE GIANBATTISTA ,  DI MARTINO ALBERTO ,  SBERNO GIAMPIERO

IPC: G11C16/16 ,  G05F3/24

公开(公告)号：ITMI20011231D0

公开(公告)日：2001-06-12

申请号：ITMI20011231

申请日：2001-06-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONIO ,  LO GIUDICE GIANBATTISTA ,  SIGNORELLO ALFREDO

IPC: G11C16/28

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

公开(公告)号：ITMI20011231A1

公开(公告)日：2002-12-12

申请号：ITMI20011231

申请日：2001-06-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONIO ,  LO GIUDICE GIANBATTISTA ,  SIGNORELLO ALFREDO

IPC: G11C16/28

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.