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    INTERFACE CIRCUIT
    1.
    发明专利
    INTERFACE CIRCUIT 失效

    公开(公告)号：JPH07263982A

    公开(公告)日：1995-10-13

    申请号：JP24959994

    申请日：1994-10-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

    IPC: H03K19/018 ,  G06J1/00 ,  H03F3/62 ,  H03F3/68

    Abstract: PURPOSE: To obtain an effective interface by providing an integrated circuit which operates with a low-voltage and a high-voltage input signal and outputs a high-voltage or low-voltage signal corresponding to them. CONSTITUTION: Cutoff circuit block 4 inhibits a 1st amplifying circuit block 2 from becoming conductive when a high-voltage output terminal operates as an input terminal. Consequently, any high-voltage signal applied to the high- voltage output terminal B operates on only a 2nd amplification block 3. A 2nd amplifying circuit block 3, on the other hand, consists of a power element which operates with a high voltage, withstands high-voltage input, and outputs a low-voltage signal. For the application of this interface circuit 1 to an industrial control unit, the 1st amplifying circuit block 2 operates relatively to an actuator, but the 2nd amplifying circuit block 3 operates relatively to a microcontroller. This block 2 can be powered directly by the same power source with the actuator and the block 3 can share a low-voltage power source with the microcontroller.

    CURRENT-MODE DIGITAL PWM CONTROL CIRCUIT
    2.
    发明专利
    CURRENT-MODE DIGITAL PWM CONTROL CIRCUIT 失效

    公开(公告)号：JPH07319565A

    公开(公告)日：1995-12-08

    申请号：JP13588595

    申请日：1995-05-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PEDRAZZINI GIORGIO ,  SCROCCHI GIUSEPPE ,  CORDINI PAOLO ,  ROSSI DOMENICO

    IPC: G05F1/56 ,  H02M1/08 ,  H02M3/155 ,  H02M3/156

    Abstract: PURPOSE: To provide a PWM control circuit for operating current mode control in a complete digital mode without necessitating the usage of any error amplifier, or excessively complicating the circuit. CONSTITUTION: This circuit includes first and second comparators COMP 1 and 2 for a sense resistance RSENSE, and a bi-directional stable logic circuit FFD 2 driven by the output of the second comparator COMP 2, which can generate a logical signal supplied to the third input of a bi-directional stable logic circuit FFD 1 for prohibiting the usage of a power switch Ml only in a preliminarily set time.

    INPUT-OUTPUT STAGE
    3.
    发明专利
    INPUT-OUTPUT STAGE 失效

    公开(公告)号：JPH07264040A

    公开(公告)日：1995-10-13

    申请号：JP26549394

    申请日：1994-10-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

    IPC: H03K19/0175

    Abstract: PURPOSE: To actualize an input/output stage which is arranged for operation with a low and a high voltage by mixed technologies. CONSTITUTION: The source-collector path of 1st and 2nd transistors(TR) M1 and M2 and the collector-source path of a 3rd TR M3 are connected across a power source in series, a diode D2 is connected in parallel to the source- collector path of the TR M2; and a circuit node A as the connection point between the cathode of the diode D2 and the collector of the TR M3 is regarded as an I/O terminal and connected to an input circuit 3, and the voltage from a drive circuit means is applied to the gate terminals of the TRs M1 to M3.

    4.
    发明专利
    未知

    公开(公告)号：DE69316215T2

    公开(公告)日：1998-04-16

    申请号：DE69316215

    申请日：1993-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

    IPC: H03K19/0175

    Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises: first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means; at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); and an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (1).

    8.
    发明专利
    未知

    公开(公告)号：DE69316215D1

    公开(公告)日：1998-02-12

    申请号：DE69316215

    申请日：1993-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

    IPC: H03K19/0175

    Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises: first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means; at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); and an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (1).

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