公开(公告)号：JPH07263982A

公开(公告)日：1995-10-13

申请号：JP24959994

申请日：1994-10-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

IPC: H03K19/018 ,  G06J1/00 ,  H03F3/62 ,  H03F3/68

Abstract: PURPOSE: To obtain an effective interface by providing an integrated circuit which operates with a low-voltage and a high-voltage input signal and outputs a high-voltage or low-voltage signal corresponding to them. CONSTITUTION: Cutoff circuit block 4 inhibits a 1st amplifying circuit block 2 from becoming conductive when a high-voltage output terminal operates as an input terminal. Consequently, any high-voltage signal applied to the high- voltage output terminal B operates on only a 2nd amplification block 3. A 2nd amplifying circuit block 3, on the other hand, consists of a power element which operates with a high voltage, withstands high-voltage input, and outputs a low-voltage signal. For the application of this interface circuit 1 to an industrial control unit, the 1st amplifying circuit block 2 operates relatively to an actuator, but the 2nd amplifying circuit block 3 operates relatively to a microcontroller. This block 2 can be powered directly by the same power source with the actuator and the block 3 can share a low-voltage power source with the microcontroller.

公开(公告)号：JPH10341588A

公开(公告)日：1998-12-22

申请号：JP11661198

申请日：1998-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： POZZONI MASSIMO ,  PEDRAZZINI GIORGIO

IPC: H02P6/16 ,  G05F20060101 ,  H02P6/06 ,  H02P6/08 ,  H02P6/182

Abstract: PROBLEM TO BE SOLVED: To detect the zerocross of the current of an inductive load without monitoring the current of an exclusive detective resistor in series with inductive load. SOLUTION: To detect the zero-cross of the current of the inductive load Ls driven in voltage mode through the half bridge consisting of a switch on high order side and a switch on low order side driven in opposite phases to each other by PWM signals, the voltage value at the output node A of the half bridge is compared with a fixed reference voltage value Vref, and the direction of the current in the inductive load Ls is judged from the comparison result. The comparison results are sampled cyclically during the period when both the switches mentioned above are off. Then, the zero cross can be detected by the inversion of the comparative value between the two continuous samplings.

公开(公告)号：JPH07319565A

公开(公告)日：1995-12-08

申请号：JP13588595

申请日：1995-05-08

Applicant: ST MICROELECTRONICS SRL

Inventor： PEDRAZZINI GIORGIO ,  SCROCCHI GIUSEPPE ,  CORDINI PAOLO ,  ROSSI DOMENICO

IPC: G05F1/56 ,  H02M1/08 ,  H02M3/155 ,  H02M3/156

Abstract: PURPOSE: To provide a PWM control circuit for operating current mode control in a complete digital mode without necessitating the usage of any error amplifier, or excessively complicating the circuit. CONSTITUTION: This circuit includes first and second comparators COMP 1 and 2 for a sense resistance RSENSE, and a bi-directional stable logic circuit FFD 2 driven by the output of the second comparator COMP 2, which can generate a logical signal supplied to the third input of a bi-directional stable logic circuit FFD 1 for prohibiting the usage of a power switch Ml only in a preliminarily set time.

公开(公告)号：JPH07264040A

公开(公告)日：1995-10-13

申请号：JP26549394

申请日：1994-10-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

IPC: H03K19/0175

Abstract: PURPOSE: To actualize an input/output stage which is arranged for operation with a low and a high voltage by mixed technologies. CONSTITUTION: The source-collector path of 1st and 2nd transistors(TR) M1 and M2 and the collector-source path of a 3rd TR M3 are connected across a power source in series, a diode D2 is connected in parallel to the source- collector path of the TR M2; and a circuit node A as the connection point between the cathode of the diode D2 and the collector of the TR M3 is regarded as an I/O terminal and connected to an input circuit 3, and the voltage from a drive circuit means is applied to the gate terminals of the TRs M1 to M3.

公开(公告)号：JPH07135517A

公开(公告)日：1995-05-23

申请号：JP9365294

申请日：1994-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIS MARCO ,  PEDRAZZINI GIORGIO

IPC: H04L29/06 ,  G06F13/40

Abstract: PURPOSE: To provide the interface circuit that is operated in compliance with any selected protocol in two kinds of protocols in response to the needs of a device that is able to be operated in both the protocols because two kinds of protocols have been used for transmission of a control signal to a control circuit conventionally, conventional devices are manufactured according to any of the protocols and this has made the burden for manufacturers. CONSTITUTION: In the case of the 1st standard (SPI), a 3rd signal (CE) fed to a pin (ADDR) is fed to a multiplexer (MUX) as it is, and in the case of the 2nd standard, the 3rd signal (CE) is fed to the multiplexer as a virtual CE signal via a decoder and a recognition signal generating means.

公开(公告)号：DE69624493T2

公开(公告)日：2003-06-26

申请号：DE69624493

申请日：1996-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO MARIA ,  POZZONI MASSIMO ,  PEDRAZZINI GIORGIO ,  RICOTTI GIULIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

公开(公告)号：DE69624493D1

公开(公告)日：2002-11-28

申请号：DE69624493

申请日：1996-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO MARIA ,  POZZONI MASSIMO ,  PEDRAZZINI GIORGIO ,  RICOTTI GIULIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

公开(公告)号：DE69322372D1

公开(公告)日：1999-01-14

申请号：DE69322372

申请日：1993-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIS MARCO ,  PEDRAZZINI GIORGIO

IPC: H04L29/06 ,  G06F13/40

Abstract: While employing the same number of dedicated pins of an IC, a self-configurable interface circuit between a control bus and the IC recognizes whether the IC is being used in a system employing an SPI or a I2CBUS protocol for the transmission to the IC of control signals through the bus. The interface circuit employs an "inner" SPI interface standard block, to a third input of which either a true CE (chip-enable) signal coming from a third wire of the bus or a virtual CE signal that is self-generated by the interface circuit in case of operation in an I2CBUS environment, is fed. The third (ADDR) pin of the IC may be connected to the CE wire of the bus in case of an SPI application or it may be biased at the supply or ground voltage for selecting one or the other of two internal addresses of the IC, when functioning in an I2CBUS environment.

公开(公告)号：DE69316215T2

公开(公告)日：1998-04-16

申请号：DE69316215

申请日：1993-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

IPC: H03K19/0175

Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises: first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means; at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); and an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (1).

公开(公告)号：DE69322372T2

公开(公告)日：1999-04-29

申请号：DE69322372

申请日：1993-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIS MARCO ,  PEDRAZZINI GIORGIO

IPC: H04L29/06 ,  G06F13/40

Abstract: While employing the same number of dedicated pins of an IC, a self-configurable interface circuit between a control bus and the IC recognizes whether the IC is being used in a system employing an SPI or a I2CBUS protocol for the transmission to the IC of control signals through the bus. The interface circuit employs an "inner" SPI interface standard block, to a third input of which either a true CE (chip-enable) signal coming from a third wire of the bus or a virtual CE signal that is self-generated by the interface circuit in case of operation in an I2CBUS environment, is fed. The third (ADDR) pin of the IC may be connected to the CE wire of the bus in case of an SPI application or it may be biased at the supply or ground voltage for selecting one or the other of two internal addresses of the IC, when functioning in an I2CBUS environment.