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公开(公告)号：JPH06260890A
公开(公告)日：1994-09-16
申请号：JP8332093
申请日：1993-04-09
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , SALI MAURO L
Abstract: PURPOSE: To obtain the high-resolution digital filter which can occupy a single small silicon space in an integrated circuit and greatly save the time of manufacturing and filter programming stages. CONSTITUTION: The high-resolution digital filter includes memory structures 3 and 4 which receive a sampled digital signal as an input signal and an adder chain 13 which has a delay block connected between the memory structures and adders 10 and 11. The adders 10 and 11 are connected to the output sides of the memory structures and convert the input signal into an output signal having specific frequency response characteristics. The memory structures include a couple of volatile memory elements, which input only part of the sample siganl.
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公开(公告)号：JPH07326195A
公开(公告)日：1995-12-12
申请号：JP5656995
申请日：1995-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , OLIVO MARCO
Abstract: PURPOSE: To prevent the occurrence of erase and change of contents of non- specified memory cells by providing a normally-open switch and a current generator to control a discharge current. CONSTITUTION: A memory cell 5 to be erased is specified. For performing the erasing, a programming voltage Vpp from a logical switch SW is connected to the cell to set a source line SRC a high voltage a normally-open switch 11 of control transistors M2 and M3 and an erase transistor M4. After completion of the erase stage, the line SRC has an erase voltage value higher than the high potential, which voltage is discharged to the ground. This causes a signal SL to be set at its high level, thus turning a switch I1 ON. This causes the voltage of the line SRC to be controlled by a current IS to continue slow discharging operation. In this way, since the discharging operation of the source line SRC is controlled to be gradually slow, the occurrence of erase/change of contents of the memory cells 5 other than the specified cell can be prevented.
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公开(公告)号：JPH07235642A
公开(公告)日：1995-09-05
申请号：JP29764694
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , GOLLA CARLA
IPC: H01L27/04 , G05F3/24 , H01L21/822
Abstract: PURPOSE: To provide a circuit configuration which can supply, with a highly simple arrangement, an accurate and stable reference potential and at the same time, can stabilize the power supply, even when temperature and process parameters vary. CONSTITUTION: This circuit includes at least one field effect transistor (M1) 103 and a resistive bias element (R) 102, connected in series with a supply power VCC between the supply power and ground, and a second field effect transistor (M2) 104 connected to the transistor 103 in such a manner that a reference potential can be extracted as a difference between the threshold voltages of the 2 transistors.
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公开(公告)号：JPH07235194A
公开(公告)日：1995-09-05
申请号：JP11995
申请日：1995-01-04
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , OLIVO MARCO , GOLLA CARLA , PADOAN SILVIA
Abstract: PURPOSE: To improve both stability and reliability by using a current mirror, a resistive divider, an amplifier stage, a source follow-up transistor TR and a resistive path connected to a reference potential. CONSTITUTION: A current mirror 3 corrects the voltage drop that is caused by the serial resistance of a bit line where its programming is ready. Then this programming is carried out by giving the voltage which varies according to the current draw of one or plural cells to be programmed to the reference potential that is obtained from reference voltage VPP via a resistive divider 2. A TR MG2 is prepared to hold a resistive path 8 reaching the ground from the programming voltage VP, and the bias current is partly subtracted from an inverted current. This subtraction part is decided by the W/L ratio of a TR contained in the mirror 3. As a result, any offset voltage that is generated on a programming line can be corrected.
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公开(公告)号：JPH06350399A
公开(公告)日：1994-12-22
申请号：JP865394
申请日：1994-01-28
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: PURPOSE: To enable the high resolution processing of a digital sampling signal by sampling an input signal based on different filtering mode or operation and adding a digital output from each filtering operation so as to reconstitute an output signal. CONSTITUTION: A 7-bit input signal S1 is impressed to the input terminal of a filter 2, which outputs a 16-bit signal S2 of address-designating the input side of a switch 3. The signal S2 directly fetched from the filter 2 alternately expresses conversion executed by the filtering section of the different transmitting function of the filter 2. The switch 3 is assigned with a task address- designating the signal S3 to an adder circuit 5 and a delay circuit 4. The circuit 4 introduces a delay time equal to a time required for the filter 2 to process a signal. Consequently, the circuit 5 adds the output of the two filtering section of the filter 2 to reconstitute a final signal.
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Patent Agency Ranking
公开(公告)号：JP2656911B2
公开(公告)日：1997-09-24
申请号：JP29764694
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , GOLLA CARLA
IPC: H01L27/04 , G05F3/24 , H01L21/822
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公开(公告)号：JPH0896590A
公开(公告)日：1996-04-12
申请号：JP22351795
申请日：1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To lengthen a lifetime without applying useless stress to a beforehand programmed bit by re-programming only the cell of a bit incapable of being compared with data to be stored. SOLUTION: When the reference signal COMPRECH of a second input terminal 4 is at 'H', the No.i bit signal SOUTi of a 16 bit word read from the cell of a fresh memory is received by a first input terminal 3 through a sense amplifier SA in a comparator 2. When the second control signal DWE of a fourth input terminal 6 is at 'H', an input terminal 9 receives a bit value DBUFi corresponding to No.i cell from a latch holding data to be written to the memory. When the result of the comparison of the signals SOUTi and DBUFi is not correct, the signal DINCOMPi of a second output terminal 13 is at 'H', and a bit to be re-programmed is indicated. Accordingly, only the specified cell of a non-volatile memory is re-programmed.
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公开(公告)号：JPH07249296A
公开(公告)日：1995-09-26
申请号：JP11795
申请日：1995-01-04
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , OLIVO MARCO , GOLLA CARLA
Abstract: PURPOSE: To improve a stability of tripping threshold value of an output signal and operating range controllability by providing a threshold value detection circuit for detecting a low threshold voltage without being affected by the change of a reference voltage. CONSTITUTION: A comparator 3 has a stable reference voltage RIF to be held at an input terminal regardless of supply voltage and temperature. By using this stable voltage reference, the tripping threshold value of the comparator 3 can be exactly set. In a normal operating state, an output signal VCCLOW from the comparator 3 is zero but when a supply voltage Vdd is reduced lower than a tripping level or a concerned circuit is turned into about 2.5V or deep power down state, for example, the voltage is increased to a voltage value Vu on a power supply line 2. Respective elements are provided with MOS transistors to be controlled by a signal PWDN according to the negative logic obtained from the external signal PWD through a negator N1. Thus, the stability of the tripping threshold value and the operation controllability can be improved.
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公开(公告)号：JPH06350398A
公开(公告)日：1994-12-22
申请号：JP780794
申请日：1994-01-27
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , CREMONESI ALESSANDRO
Abstract: PURPOSE: To enable the high resolution processing of a coded digital sampling signal by dividing an inputted sampling signal into at least two parts and filtering each part without regard to the other parts by the digital filter of each to reconstitute an output sampling signal. CONSTITUTION: A digital signal S with a 9-bit code is impressed to a decoder D to select eight highest order digit bits to output a signal S1 to a first programmable digital filter (PFP) 2 and an adder 4. The adder 4 receives a pit a0 with the maximum weight of the lowest order digit part of the digital signal S selected by the decoder D at the other input terminal and generates an 8-bit signal S2 to input as an address signal to the address terminal of second PFP 2. Output from two PFP 2 are added by an adder 5 to correctly reconstitute an output signal. Consequently a signal with a high dynamic range is given high resolution processing.
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公开(公告)号：DE69622149T2
公开(公告)日：2002-11-28
申请号：DE69622149
申请日：1996-03-21
Applicant: ST MICROELECTRONICS SRL
Inventor： BRANCHETTI MAURIZIO , CONCI ARMANDO , GOLLA CARLA
IPC: G06F11/10
Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device being set up as a multi-sectors memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by acting said selection circuitry, whenever the device fails an operation test. The use of a Hamming code of error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.
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