-
公开(公告)号：JPH0846487A
公开(公告)日：1996-02-16
申请号：JP16657095
申请日：1995-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLE FESTE SANDRO , BIANCHESI MARCO , CREMONESI ALESSANDRO
Abstract: PURPOSE: To satisfy timewise limitation conditions to filter components with a filter having serial architecture with a finite impulse response(FIR) while having a simple controller. CONSTITUTION: This oversampling digital filter is composed of a memory means M1 for coefficients, memory means M2 for sampling signals to be filtered, multiplier MU connected to the output terminals of memory means M1 and M2, accumulator AC connected to the output terminal of that multiplier MU, and simple controller CU for controlling elements based on a clock signal CLK received at the input terminal of that accumulator.
-
公开(公告)号：JPH11252187A
公开(公告)日：1999-09-17
申请号：JP34611798
申请日：1998-12-04
Applicant: ST MICROELECTRONICS SRL
Inventor： BIANCHESSI MARCO , DALLE FESTE SANDRO , SERINA NADIA , ANGELICI MARCO
Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit for decoding an input digital signal or a stream by generating a signal which is phase-locked by a digital input signal encoded in accordance with two-phase modulation from a master clock signal. SOLUTION: In the case of a two phase modulation digital input stream, a prescribed characteristic is observed. Namely, an input signal is sampled by the drop edge of a clock signal Ck. Thus, the triplet of samples which always have the same logic values are generated. The characteristic can be used for intervention in the division (division) of the master clock signal Ck and for correcting a synchronizing signal Synk generated in a mode where the phase and the consistency of an input digital signal Input are maintained. Thus, correction can substantially and instantaneously be executed and erroneous shift of producing decoding errors can be prevented.
-
公开(公告)号：JP2000059224A
公开(公告)日：2000-02-25
申请号：JP9750699
申请日：1999-04-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BIANCHESSI MARCO , DALLE FESTE SANDRO , SERINA NADIA , ANGELICI MARCO , OSNATO FABIO
Abstract: PROBLEM TO BE SOLVED: To provide a sigma delta modulator securing the stability of a system and simplifying constitution. SOLUTION: The modulator is provided with at least two integration stages A, a comparator generating a signal at a logical level +1 in the case that an inputted signal is positive and a signal of a logical value -1 in the case that the inputted signal is negative without regard to its absolute value, and an adding means adding a feedback signal filtered by at least one low-pass filter B to a signal to be outputted to the last of the stage A. In addition, the modulator is provided with a second comparator which is commonly connected with the output end of the first comparator and outputs a logical signal being a positive value in the case that an inputted signal is positive and being a negative value in the case that the inputted signal is negative, the logical signal is increased in the case that the input signal exceeds one of increasing values or a prescribed threshold larger than it and an outputted logical signal is provided to the filter B.
-
4.发明专利
公开(公告)号：JPH11194839A
公开(公告)日：1999-07-21
申请号：JP30293198
申请日：1998-10-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ANGELICI MARCO , DALLE FESTE SANDRO , SERINA NADIA , BIANCHESSI MARCO
IPC: H01L27/04 , G05F1/10 , G05F1/56 , G05F3/26 , H01L21/822
Abstract: PROBLEM TO BE SOLVED: To make it possible to generate a low-noise symmetrical reference voltage subjected to temperature compensation by allowing current of a differential pair from a voltage-current converting stage and a current mirror to output two symmetrical reference voltages in a pair of mutual resistance feedback operational amplifiers. SOLUTION: The voltage current converting stage converts a reference voltage which is low noise of an external supply source and also does not depend on a temperature into a current I1. The current mirror of MOSS transistors M1 to M5 generates a current I1 of a differential pair which is a replica of the current I1. Two currents I1 of the currents I1 of the differential pair respectively flow into a pair of mutual resistance feedback operational amplifiers OPABUF and output two symmetrical voltages VH and VL with the voltage VA of an analog ground node A which coincides with voltage VBG as reference. Thermal compensation of the voltages VH and VL is realized according to an interlace type physical layout so as to show the same thermal inclination that is compensated with the ratio of resistance R2/R1.
-
公开(公告)号：DE69809710T2
公开(公告)日：2003-09-18
申请号：DE69809710
申请日：1998-04-03
Applicant: ST MICROELECTRONICS SRL
Inventor： BIANCHESSI MARCO , DALLE FESTE SANDRO , SERINA NADIA , ANGELICI MARCO , OSNATO FABIO
Abstract: A sigma-delta modulator of second or higher order, comprising two or more integrating stages (A), a comparator (Comp) in cascade to the integration stages, generating a signal of logic level +1 when the input signal is positive or of logic value -1 when the input signal is negative, regardless of its absolute value, a feedback line comprising at least a low-pass filter (B) and adder means adding a feedback signal, filtered by the low-pass filter (B) to the signal output by the last of the integrating stages (A), further comprises a second comparator (Comp2) having an input connected in common to the input of the first comparator (Comp) and outputting a logic signal of positive value when the input signal is positive and of negative value when the input signal is negative, but of increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value and the output logic signal being fed to the input of the low-pass filter (B).
-
Patent Agency Ranking
公开(公告)号：DE69428526D1
公开(公告)日：2001-11-08
申请号：DE69428526
申请日：1994-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLE FESTE SANDRO , BIANCHESI MARCO , CREMONESI ALESSANDRO
Abstract: The oversampling digital filter with Finite Impulse Response is implemented by means of a serial structure comprising a memory means (M1) for the coefficients, a memory means (M2) for the signal samples to be filtered, a multiplier (MU) connected to the output of said memories (M1, M2), an accumulator (AC) connected to the output of the multiplier (MU), and a simple control unit (CU) which controls said elements on the basis of a clock signal (CLK) which it receives at input.
-
公开(公告)号：DE69724631D1
公开(公告)日：2003-10-09
申请号：DE69724631
申请日：1997-12-04
Applicant: ST MICROELECTRONICS SRL
Inventor： BIANCHESSI MARCO , DALLE FESTE SANDRO , SERINA NADIA , ANGELICI MARCO
-
公开(公告)号：DE69527790D1
公开(公告)日：2002-09-19
申请号：DE69527790
申请日：1995-09-29
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLE FESTE SANDRO , BIANCHESSI MARCO , SERINA NADIA
Abstract: The invention concerns a microphone device of the digital type, which comprises at least one analog input interface (IN) having input terminals arranged to receive an analog voltage signal. This microphone device further comprises at least one digital output interface (OUT) having at least one input terminal arranged to receive a digital voltage signal, and at least first and second output terminals for transmitting said digital voltage signal in a serial format. Lastly, the microphone device includes at least one converter block (C) connected between the input interface (IN) and the output interface (OUT).
-
公开(公告)号：DE69710467D1
公开(公告)日：2002-03-21
申请号：DE69710467
申请日：1997-10-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ANGELICI MARCO , DALLE FESTE SANDRO , SERINA NADIA , BIANCHESSI MARCO
Abstract: Generation of symmetrical temperature compensated reference voltages in mixed type integrated circuits with a superior PSRR includes the use of a voltage-to-current conversion stage of a temperature independent bandgap voltage for producing eventually a differential pair of currents that are input to a pair of transresistance feedback operational amplifiers the feedback resistors of which are integrated in an interlaced form with a resistor employed in said conversion stage.
-
公开(公告)号：DE69809710D1
公开(公告)日：2003-01-09
申请号：DE69809710
申请日：1998-04-03
Applicant: ST MICROELECTRONICS SRL
Inventor： BIANCHESSI MARCO , DALLE FESTE SANDRO , SERINA NADIA , ANGELICI MARCO , OSNATO FABIO
Abstract: A sigma-delta modulator of second or higher order, comprising two or more integrating stages (A), a comparator (Comp) in cascade to the integration stages, generating a signal of logic level +1 when the input signal is positive or of logic value -1 when the input signal is negative, regardless of its absolute value, a feedback line comprising at least a low-pass filter (B) and adder means adding a feedback signal, filtered by the low-pass filter (B) to the signal output by the last of the integrating stages (A), further comprises a second comparator (Comp2) having an input connected in common to the input of the first comparator (Comp) and outputting a logic signal of positive value when the input signal is positive and of negative value when the input signal is negative, but of increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value and the output logic signal being fed to the input of the low-pass filter (B).
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.021 seconds)
