-
公开(公告)号：JP2000174626A
公开(公告)日：2000-06-23
申请号：JP33007299
申请日：1999-11-19
Applicant: ST MICROELECTRONICS SRL
Inventor： OTTINI DANIELE , BRUCCOLERI MELCHIORRE , BOLLATI GIACOMINO , DEMICHELI MARCO
Abstract: PROBLEM TO BE SOLVED: To provide a flash analog/digital converter capable of outputting a temperature measurement digital code. SOLUTION: This flash analog/digital converter is provided with a bank composed of comparators (COMPi) provided with differential output for generating a temperature measurement code and 3-input (A, B and C) logical NOR gates (NORj) and is provided with a passive interface respectively composed of the plural pieces of voltage dividers (Ra-Rb) connected between the non- inverted output (out-p) of the respective comparators (COMPi) and the inverted output (out-n) of the comparators (COMPi+1) of the higher order of the bank. The corresponding logical NOR gate (NORj) of the bank is provided with first input (A) connected to the inverted output (out-n) of the respective comparators (COMPi-1), second input (B) connected to the non-inverted output (out-p) of the comparators (COMPi) of the higher order and third input (C) connected to the intermediate tap of the voltage dividers (Ra-Rb).
-
2.发明专利
公开(公告)号：JP2000173186A
公开(公告)日：2000-06-23
申请号：JP34210599
申请日：1999-12-01
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI MARCO , OTTINI DANIELE , SAVO ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To prevent the generation of accidental patterns in a frequency domain by individually controlling two identical offest compensating circuits for two ATOD converters. SOLUTION: An interleave type ATOD converter is constituted of two identical analog digital converters, i.e., one for even bit EVEN-S signal path and one for ATOD-EVEN and odd bit ODD-S signal path and an ATOD-ODD. The offsets of digital analog converters included in the ATOD-EVEN and the ATOD-ODD are independently compensated for by the loop constituted of offset compensation stages and OFFSET-EVEN-STAGE and OFFSET-ODD- STAGE controlled by a digital post process blocks through a dedicated digital analog converter DA-OFF-E and a DAC-OFF-O.
-
公开(公告)号：JP2000013185A
公开(公告)日：2000-01-14
申请号：JP13422999
申请日：1999-05-14
Applicant: ST MICROELECTRONICS SRL
Inventor： DE MICHELI MARCO , PORTALURI SALVATORE , BOLLATI GIACOMINO , BRUCCOLERI MELCHIORRE
Abstract: PROBLEM TO BE SOLVED: To shorten transconductance stable time after a request for changing the interruption frequency of a filter by installing a feedback loop between the output/input of a transconductor connected to DAC so that reference current is set and making reference current which is set by DAC into a mirror image. SOLUTION: In a master section circuit, output current IR from DAC 7, which is set by reference current generated by a current source 8 and digital word FC-WORD, is made into a mirror image by a PMOS transistor 20 which is diode-connected. Current which is made into the mirror image is sent later from a PMOS transistor 21 to an NMOS transistor 22. It is made into the mirror image in an NMOS transistor 23. The drain terminal of the transistor 23 is connected to a node 6 and a capacitor 5 is connected to the node 6. Thus, the transistor 22 sets the current of the transistor 23.
-
公开(公告)号：JPH1174765A
公开(公告)日：1999-03-16
申请号：JP17473498
申请日：1998-06-22
Applicant: ST MICROELECTRONICS SRL
Inventor： CELANT LUCA , DEMICHELI MARCO , BRUCCOLERI MELCHIORRE , RIGAZIO LUCA
IPC: H03K3/0231 , H03K3/282
Abstract: PROBLEM TO BE SOLVED: To operate with power supply voltage that is lower than normal power supply voltage by configuring a connection circuit means with a differential amplifier which has a differential output terminal that is connected to the bases of two transistors respectively. SOLUTION: A balanced differential amplifier is provided between two transistors Q1 and Q2 as a connecting means for positive feedback. The differential amplifier has two npn transistors T3 and T4, interconnects their emitters, also connects its current Ip to a ground terminal through a current source G5 which is adjusted by the voltage of a control terminal SW, connects their collectors to a power supply terminal Vcc through respectively different resistance R3 and R4 and connects their bases to the collectors of the transistors Q2 and Q1 respectively. The collectors of the transistors T3 and T4 are further connected to bases of the transistors Q2 and Q1 respectively and also each collector can be taken out as an output terminal Vout of this oscillator.
-
公开(公告)号：JP2000195169A
公开(公告)日：2000-07-14
申请号：JP35109399
申请日：1999-12-10
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMICHELI MARCO , BRUCCOLERI MELCHIORRE , MALFA MAURIZIO , BOLLATI GIACOMINO
Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for pre-compensating interference between marks in a large capacity storage device. SOLUTION: This device supplys a digital data stream (I) and a clock signal (Ck) to be stored in a 1st circuit and also makes the 1st circuit(CC1) output a pair of digital streams (N, R). Further, the digital streams (N, R) and the clock signal (Ck) are supplied to a 2nd circuit (DC1), and the 2nd circuit outputs a digital data stream (O) directed to a write head. In such a case, by sampling the two digital streams (N, R) by a pair of flip-flops (FN2, FR2) and also re- coupling the signals outputted from the pair of flip-flops (FN1, FR2) with a digital data stream (O) via a logical XOR gate (X1), the device delays a transition immediately following a preceding transition by a predetermined time interval (Δwp).
-
Patent Agency Ranking
公开(公告)号：JP2000166237A
公开(公告)日：2000-06-16
申请号：JP11667499
申请日：1999-04-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , OTTINI DANIELE , DEMICHELI MARCO , BOLLATI GIACOMINO
Abstract: PROBLEM TO BE SOLVED: To reduce higher harmonics and dynamic distortion by receiving a differential logical synchronizing signal at the input terminal of a timing circuit, and supplying the first differential timing signal to a track-and-hold stage and the second differential timing signal to a flip flop, respectively. SOLUTION: Differential logical synchronizing signals Clk+, Clk- are received at the input terminal of a timing circuit, and the first differential timing signals TClK+, TClK- are outputted to a differential track-and-hold stage TandH at an output terminal. The second differential timing signals DClK+, DClK- are outputted to a flip flop LATCH-ECL at the output terminal of the timing circuit. The differential track-and-hold stage TandH tracks differential analog input signals IN+, IN- during the tracking phase of the first differential timing signals TClK+, TClK-. The differential flip flop LaATCH-ECL outputs the third differential logical control signals S+, S-.
-
公开(公告)号：JPH1186459A
公开(公告)日：1999-03-30
申请号：JP19573198
申请日：1998-07-10
Applicant: ST MICROELECTRONICS SRL
Inventor： CELANT LUCA , DE MICHELI MARCO , BRUCCOLERI MELCHIORRE , RIGAZIO LUCA
Abstract: PROBLEM TO BE SOLVED: To prevent locking caused by injection of two oscillators due to stray current in an integrated circuit. SOLUTION: The integrated circuit has two phase lock groups, R-PLL, W-PLL, and each of these phase lock groups has its own oscillators OSC-1, OSC-2. The oscillator OSC-2 of one of these phase lock groups, W-PLL, is coupled with a noise generator N-GEN. And a means TM which operates this noise generator N-GEN is installed so that injected noise randomly changes the frequency of the oscillator OSC-2 of the above one phase lock group when the other phase lock group is in operation.
-
公开(公告)号：DE60217881D1
公开(公告)日：2007-03-15
申请号：DE60217881
申请日：2002-11-28
Applicant: ST MICROELECTRONICS SRL
Inventor： RADICE FRANCESCO , BRUCCOLERI MELCHIORRE
Abstract: The invention relates to a circuit device (1) for realising a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive (L) and capacitive (C) components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component (L,C) of the network is formed by cascade connecting a first (2) and a second (3) transconductance (Gm1,Gm2) integrator with each other.
-
公开(公告)号：DE69825060D1
公开(公告)日：2004-08-19
申请号：DE69825060
申请日：1998-12-17
Applicant: ST MICROELECTRONICS SRL
Inventor： BOLLATI GIACOMINO , ALINI ROBERTO , OTTINI DANIELE , BRUCCOLERI MELCHIORRE
IPC: H03H11/04
Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current (iz), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current (iz) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.
-
公开(公告)号：DE69519663T2
公开(公告)日：2001-04-26
申请号：DE69519663
申请日：1995-03-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , VAI GIANFRANCO , PORTALURI SALVATORE , DEMICHELI MARCO
Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.
-
-
-
-
-
-
-
-
-
Search Results
40
records
(took 0.021 seconds)
