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公开(公告)号：JPH07142949A
公开(公告)日：1995-06-02
申请号：JP11291294
申请日：1994-05-26
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: PURPOSE: To obtain the digital control circuit for amplifier gain control with low power consumption at a low cost. CONSTITUTION: The control circuit includes a peak detector 2 and a gain control stage 3 connected to an input terminal of a reception channel 1 via a coded signal rectifier circuit. The gain control stage includes a digital comparator 6 and two input terminals are connected respectively to the peak detector and an output terminal of a memory 8. The output terminal of the gain control stage 3 is connected to a gain control terminal of the amplifier stage FA. The content of addresses selectable in the memory 8 includes a prescribed peak level in a coded form.
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公开(公告)号：JP2001249161A
公开(公告)日：2001-09-14
申请号：JP2001010262
申请日：2001-01-18
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO
Abstract: PROBLEM TO BE SOLVED: To improve discrimination between normality and defect of a device, and heighten yield. SOLUTION: This test method comprises a process for forming first and second measuring transistors of n-channel and p-channel in each integrated circuit, a process for biasing the measuring transistors in a breaking region, a process for measuring sub-threshold currents of the measuring transistors, a process for calculating sub-threshold currents per unit channel area relative to the n-channel transistor and the p-channel transistor from the sub-threshold currents and channel areas of the measuring transistors, a process for obtaining the total channel area of the n-channel transistor and the p-channel transistor in the breaking state when the integrated circuits are in the steady state and in the idling state, a process for calculating the products between the total channel area and the sub-threshold currents per unit channel area, a process for calculating an absorption current by the integrated circuits in the steady state and in the idling state by adding the products and a process for obtaining a threshold current by adding an increase portion of a current prescribed beforehand to the absorption current.
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公开(公告)号：JP2001133510A
公开(公告)日：2001-05-18
申请号：JP2000271802
申请日：2000-09-07
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO
Abstract: PROBLEM TO BE SOLVED: To provide a method requiring no highly sensitive detection circuit and no expensive device in particular, in a method for measuring a current when an integrated circuit having high element density is inspected. SOLUTION: The CMOS integrated circuit is inspected by a process for preparing the integrated circuit in a static condition, a process for biasing a P-type main body area 9 in a potential VBBN more negative than a negative electrode VSS of an electric power source and biasing an N-type main body area 12 in a potential VBBP more positive than a positive electrode VDD of the power source, a process for setting a current threshold value Ith, a process for measuring the absorbed current IDDQ, a process for comparing the measured current IDDQ with the threshold value current Ith, and a process for accepting the integrated circuit when the measured current IDDQ is determined to be smaller than the threshold value current Ith as a result of comparison therein, and for rejecting the integrated circuit when the measured current IDDQ is determined to be larger than the threshold value current Ith in the comparison.
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公开(公告)号：DE69517693T2
公开(公告)日：2001-03-01
申请号：DE69517693
申请日：1995-12-29
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CONFALONIERI PIERANGELO
Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, is described. The cells define circuit modules (11) in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips (12, 13; 12, 14) for connection to the supply (Vcc, Vss), at least one of which is in contact (12p, 13n; 14n) with the source regions (4, 5) of MOS transistors of the CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library described also provides a group (1) of cells in which there is provided at least one additional trace which defines an additional strip (15) for connection to the outside (Vb) which is in contact (15s) with the body regions of the MOS transistors of the CMOS pair.
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公开(公告)号：DE69316880D1
公开(公告)日：1998-03-12
申请号：DE69316880
申请日：1993-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.
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Patent Agency Ranking
公开(公告)号：DE69926126T2
公开(公告)日：2006-05-11
申请号：DE69926126
申请日：1999-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO
Abstract: A CMOS integrated circuit is tested by the following steps: supplying the integrated circuit in static conditions, biasing the p-type body regions (9) with a potential (VBBN) more negative than the negative pole (VSS) of the supply and the n-type body regions (12) with a potential (VBBP) more positive than the positive pole (VDD) of the supply, setting a current threshold value (Ith), measuring the current (IDDQ) absorbed, comparing the current (IDDQ) measured with the threshold current (Ith), accepting or rejecting the integrated circuit if the comparison shows that the current (IDDQ) measured is less than or is greater than the threshold value (Ith), respectively.
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公开(公告)号：DE69517693D1
公开(公告)日：2000-08-03
申请号：DE69517693
申请日：1995-12-29
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CONFALONIERI PIERANGELO
Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, is described. The cells define circuit modules (11) in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips (12, 13; 12, 14) for connection to the supply (Vcc, Vss), at least one of which is in contact (12p, 13n; 14n) with the source regions (4, 5) of MOS transistors of the CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library described also provides a group (1) of cells in which there is provided at least one additional trace which defines an additional strip (15) for connection to the outside (Vb) which is in contact (15s) with the body regions of the MOS transistors of the CMOS pair.
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公开(公告)号：DE69316880T2
公开(公告)日：1998-05-28
申请号：DE69316880
申请日：1993-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.
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公开(公告)号：DE69926126D1
公开(公告)日：2005-08-18
申请号：DE69926126
申请日：1999-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO
Abstract: A CMOS integrated circuit is tested by the following steps: supplying the integrated circuit in static conditions, biasing the p-type body regions (9) with a potential (VBBN) more negative than the negative pole (VSS) of the supply and the n-type body regions (12) with a potential (VBBP) more positive than the positive pole (VDD) of the supply, setting a current threshold value (Ith), measuring the current (IDDQ) absorbed, comparing the current (IDDQ) measured with the threshold current (Ith), accepting or rejecting the integrated circuit if the comparison shows that the current (IDDQ) measured is less than or is greater than the threshold value (Ith), respectively.
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公开(公告)号：DE60037242D1
公开(公告)日：2008-01-10
申请号：DE60037242
申请日：2000-05-04
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO
Abstract: The circuit system comprises an integrated circuit which is one of a family of equivalent integrated circuits that comprises a first-generation integrated circuit (IC1g') operating at the supply voltage of the circuit system (V) and at least one subsequent-generation integrated circuit (IC2g') having a portion (A') operating at a lower voltage. The first-generation integrated circuit (IC1g') has a direct electrical connection (SC) between one (VDD1g) of the supply terminals and another terminal (VDD2g). The subsequent-generation integrated circuit (IC2g') has a voltage reducer with regulator (RG) the output of which is connected to the said other terminal (VDD2g). A filter capacitor (C) is connected between the said other terminal (VDD2g) and one (VSS) of the supply terminals.
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