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公开(公告)号：JPH0715980A
公开(公告)日：1995-01-17
申请号：JP16278994
申请日：1994-06-21
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , CONFALONIERI PIERANGELO , CRIPPA CARLO
Abstract: PURPOSE: To provide a voltage multiplier circuit of a stable output voltage, capable of practically taking out a relatively high output current which is in dependent of the respective kinds of parameters. CONSTITUTION: Error signals which are the displays of the differences between a reference voltage VRIF and an output voltage Vsur are generated, and the error signals are used for driving a transistor which acts as a switch for grounding a charge transfer capacitance C1 . Thus, the output voltage Vsur of this voltage multiplier is maintained fixed.
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公开(公告)号：JPH07142949A
公开(公告)日：1995-06-02
申请号：JP11291294
申请日：1994-05-26
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: PURPOSE: To obtain the digital control circuit for amplifier gain control with low power consumption at a low cost. CONSTITUTION: The control circuit includes a peak detector 2 and a gain control stage 3 connected to an input terminal of a reception channel 1 via a coded signal rectifier circuit. The gain control stage includes a digital comparator 6 and two input terminals are connected respectively to the peak detector and an output terminal of a memory 8. The output terminal of the gain control stage 3 is connected to a gain control terminal of the amplifier stage FA. The content of addresses selectable in the memory 8 includes a prescribed peak level in a coded form.
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Patent Agency Ranking
公开(公告)号：DE69316880D1
公开(公告)日：1998-03-12
申请号：DE69316880
申请日：1993-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.
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公开(公告)号：DE69432727D1
公开(公告)日：2003-07-03
申请号：DE69432727
申请日：1994-06-17
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , CONFALONIERI PIERANGELO , CRIPPA CARLO
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公开(公告)号：DE69316880T2
公开(公告)日：1998-05-28
申请号：DE69316880
申请日：1993-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.
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公开(公告)号：IT201700088977A1
公开(公告)日：2019-02-02
申请号：IT201700088977
申请日：2017-08-02
Applicant: ST MICROELECTRONICS SRL
Inventor： CRIPPA CARLO , BASSOLI ROSSELLA
IPC: G06F3/01 , G05B19/045
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公开(公告)号：ITUB20153317A1
公开(公告)日：2017-03-01
申请号：ITUB20153317
申请日：2015-09-01
Applicant: ST MICROELECTRONICS SRL
Inventor： BASSOLI ROSSELLA , CRIPPA CARLO
IPC: G01C17/38
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