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    PREPARATION OF SEMICONDUCTOR DEVICE WITH EMBEDDED JOINING
    1.
    发明专利
    PREPARATION OF SEMICONDUCTOR DEVICE WITH EMBEDDED JOINING 失效

    公开(公告)号：JPH0846069A

    公开(公告)日：1996-02-16

    申请号：JP7625895

    申请日：1995-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

    IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866

    Abstract: PURPOSE: To reduce the dependency on the process parameters of the concentration and/or depth of a buried region, by allowing a second impurity addition stage to have a first sub-step for performing implantation with a low energy and a second sub-step for performing implantation by a low amount of addition and a high energy. CONSTITUTION: When a semiconductor device with a buried junction is manufactured, the impurity in a first format (arsenic) and a second formal (boron) is successively introduced into a silicon chip by the first and second impurity addition stages. An introduced impurity is diffused by a high-temperature treatment, thus forming first and second regions 32 and 33. The amount of impurity to be added and an implantation energy are at a level so that the conduction format (N) of the first region 32 cannot be canceled or inverted, and a concentration at the second region 33 essentially depends on only a second implantation.

    6.
    发明专利
    未知

    公开(公告)号：DE69505348D1

    公开(公告)日：1998-11-19

    申请号：DE69505348

    申请日：1995-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE PETRO RICCARDO ,  PALMIERI MICHELE ,  GALBIATI PAOLA ,  CONTIERO CLAUDIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A high voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on enriched drain regions (16) are formed by implanting doping material (N) in the silicon through apertures in the field oxide (11) obtained with a selective anisotropic etching by utilising as a mask the strips of polycrystaline silicon (14) which serve as gate electrodes and field electrodes.

    9.
    发明专利
    未知

    公开(公告)号：DE69415500D1

    公开(公告)日：1999-02-04

    申请号：DE69415500

    申请日：1994-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

    IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866 ,  H01L21/82

    Abstract: A method is disclosed for forming a first region (32) with conductivity of a first type (N) and second, buried region (30) with conductivity of a second type (P) which forms a junction with the first region (32). By first and second doping steps, impurities of a first (As) and a second (B) type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first (32) and second (30) regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region (32), and such that the concentration in the second region (30) will be substantially due to the second implantation step only. This process is compatible with a CMOS-process. The buried junction can be used for a Zener diode, a vertical bipolar transistor or a JFET.

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