公开(公告)号：JP2000244257A

公开(公告)日：2000-09-08

申请号：JP2000034045

申请日：2000-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

Abstract: PROBLEM TO BE SOLVED: To provide a digital input PWM power amplifier which is operated with high efficiency and by a comparatively low switching frequency. SOLUTION: This digital input PWM power amplifier is provided with an over-sampling noise shaping circuit, a first bus for transmitting the maximum digit bit (most significant bit) of a first number D, the second bus for transmitting the minimum digit bit (least significant bit) of the second number S and first and second PCM/PWM converters for respectively receiving the supply of first and second number bits and outputting PWM signals (MSBdig and LSBdig). The PWM signal(MSBdig) outputted by the first converter is added to the PWMsignal(LSBdig) outputted by the second one on the reverse input node(-) of an output power stage.

公开(公告)号：JP2000151299A

公开(公告)日：2000-05-30

申请号：JP31906499

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To provide a class D power amplifier which can process an analog or digital input signal without the need to generate a reference waveform. SOLUTION: The amplifier has two identical amplification modules. Each module has a switching output operational amplifier (O1) equipped with a voltage noninverted input terminal (In+), a current mode inverted input terminal (In-), and a loop filter which outputs a signal composed substantially of a triangular waveform and actualizes a single or plural gradient integrator, a cascade (C1) composed of a logic inverter or plural logic inverters which are coupled with the output terminal of the integrator and output logic PWM signals, an output power stage (P1) which converts the logic PWM signal to a PWM signal and switches between the potentials of two supply rails of the circuit, and a feedback resistance (Rf) which connects the output terminal of a power stage (P1) to the inverted input terminal (In-) of the operational amplifier (O1).

公开(公告)号：DE69919500T2

公开(公告)日：2005-09-08

申请号：DE69919500

申请日：1999-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

Abstract: A digital input PWM power amplifier comprises: an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number M of bits at a certain bit rate (Fin) and outputting pulse code modulated digital data organized in words of a smaller number N of bits at a multiple bit rate (Fin*K); a first bus transmitting a first number (P) of most significant bits (MSB) of said N bit words output from said first circuit and a second bus transmitting a second number (S) of least significant bits of said N bit words output from said first circuit; first and second PCM/PWM converters, respectively fed with said first and second number of bits transmitted through said first and said second bus, each converter including a counter driven by a clock signal (Fclock) of frequency equal to the product of the bit rate (Fin*K) of the MSB and LSB bits transmitted on the respective bus and the square of the respective number of bits (P, S) generating reference digital words composed of said respective number of bits (P, S), defining ramps of digital values with a frequency identical to said multiple bit rate (Fin*K), and a digital comparator receiving through a first input said reference digital words and through a second input the respective first and second number of bits (MSB, LSB) and outputting a respective PWM signal (MSBdig, LSBdig); the PWM signal (MSBig) output by said first converter, being summed to the so attenuated PWM signal (LSBdig) output by said second converter on the inverting input node (-) of said output power stage.

公开(公告)号：DE602005018012D1

公开(公告)日：2010-01-14

申请号：DE602005018012

申请日：2005-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSO ANTONIO ,  MERONI CRISTIANO ,  BOTTI EDOARDO

IPC: H03M1/18

Abstract: The dynamic range of operation of a digital-to-analog converter of an audio system, including at least first and second subsets of individually selectable elementary current sources for delivering analog output current contributions, a code conversion circuit for selecting elementary current sources of said subsets first and second in function of the value of each sampled code of a pulse code modulated input signal, is embedded by multiplying by a certain factor incoming digital codes of said pulse code modulated input signal after their value has remained lower than a predefined threshold value for a certain period of time and for as long as their value equals or surpasses than said threshold value and correspondingly scaling and de-scaling by the same factor the amplitude of said analog output current contributions produced by the elementary current sources of said two subsets.

公开(公告)号：DE60026962T2

公开(公告)日：2007-04-05

申请号：DE60026962

申请日：2000-09-01

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  CLERIS MAURO ,  GROSSO ANTONIO

IPC: G01R23/20

Abstract: The present invention relates to an adjustable harmonic distortion detector comprising a clock signal source (9), means for the detection of a first period of evaluation (T1) and means for the detection of a second period of evaluation (T2). Said detector has the characteristic that a first block (12) memorizes a number equal to the clock pulses present in said first period of evaluation (T1), a multiplier block (16) makes a multiplication between said number stored in said first block (T1) and a multiplicative factor during said second period of evaluation (T2), a second block (23) memorizes the outcome, said second block (23) adapted to generate an output signal (27) when said outcome in said second block (23) is equal to zero.

公开(公告)号：DE69829852D1

公开(公告)日：2005-05-25

申请号：DE69829852

申请日：1998-11-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

IPC: H03F3/217

Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

公开(公告)号：DE60035108D1

公开(公告)日：2007-07-19

申请号：DE60035108

申请日：2000-08-29

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

IPC: H03F3/217 ,  H03F1/30 ,  H03F3/45

Abstract: A power amplification apparatus receiving in input an enable signal (En) and an input square wave signal (C) is described. The apparatus comprises a device (6) receiving the input square wave signal (C) and the enable signal (En) and which produces a new enable signal (Ens) of the apparatus which is synchronized with a rise or down front of the input square wave signal (C), so that an output square wave signal (Vo) of the apparatus, which is normally shifted of a certain period fraction with respect to the square wave signal (C) in input to the apparatus, has the first (Ti) and the last (Tf) pulses which have a duration equal to a period fraction of the output square wave signal (Vo).

公开(公告)号：DE60029097D1

公开(公告)日：2006-08-10

申请号：DE60029097

申请日：2000-08-04

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSO ANTONIO ,  BOTTI EDOARDO

IPC: G06F1/025 ,  H03F3/217 ,  H03K7/08 ,  H03L7/00 ,  H03M1/68 ,  H03M1/82

公开(公告)号：DE60026962D1

公开(公告)日：2006-05-18

申请号：DE60026962

申请日：2000-09-01

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  CLERIS MAURO ,  GROSSO ANTONIO

IPC: G01R23/20

Abstract: The present invention relates to an adjustable harmonic distortion detector comprising a clock signal source (9), means for the detection of a first period of evaluation (T1) and means for the detection of a second period of evaluation (T2). Said detector has the characteristic that a first block (12) memorizes a number equal to the clock pulses present in said first period of evaluation (T1), a multiplier block (16) makes a multiplication between said number stored in said first block (T1) and a multiplicative factor during said second period of evaluation (T2), a second block (23) memorizes the outcome, said second block (23) adapted to generate an output signal (27) when said outcome in said second block (23) is equal to zero.

公开(公告)号：DE69919500D1

公开(公告)日：2004-09-23

申请号：DE69919500

申请日：1999-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

Abstract: A digital input PWM power amplifier comprises: an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number M of bits at a certain bit rate (Fin) and outputting pulse code modulated digital data organized in words of a smaller number N of bits at a multiple bit rate (Fin*K); a first bus transmitting a first number (P) of most significant bits (MSB) of said N bit words output from said first circuit and a second bus transmitting a second number (S) of least significant bits of said N bit words output from said first circuit; first and second PCM/PWM converters, respectively fed with said first and second number of bits transmitted through said first and said second bus, each converter including a counter driven by a clock signal (Fclock) of frequency equal to the product of the bit rate (Fin*K) of the MSB and LSB bits transmitted on the respective bus and the square of the respective number of bits (P, S) generating reference digital words composed of said respective number of bits (P, S), defining ramps of digital values with a frequency identical to said multiple bit rate (Fin*K), and a digital comparator receiving through a first input said reference digital words and through a second input the respective first and second number of bits (MSB, LSB) and outputting a respective PWM signal (MSBdig, LSBdig); the PWM signal (MSBig) output by said first converter, being summed to the so attenuated PWM signal (LSBdig) output by said second converter on the inverting input node (-) of said output power stage.