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    PWM BRIDGE AMPLIFIER EQUIPPED WITH INPUT NETWORK WHOSE TYPE CAN BE SPECIFIED FOR ANALOG OF DIGITAL INPUT REQUIRING NO TRIANGULAR WAVE GENERATOR
    1.
    发明专利
    PWM BRIDGE AMPLIFIER EQUIPPED WITH INPUT NETWORK WHOSE TYPE CAN BE SPECIFIED FOR ANALOG OF DIGITAL INPUT REQUIRING NO TRIANGULAR WAVE GENERATOR 失效

    公开(公告)号：JP2000151299A

    公开(公告)日：2000-05-30

    申请号：JP31906499

    申请日：1999-11-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

    IPC: H03F3/217

    Abstract: PROBLEM TO BE SOLVED: To provide a class D power amplifier which can process an analog or digital input signal without the need to generate a reference waveform. SOLUTION: The amplifier has two identical amplification modules. Each module has a switching output operational amplifier (O1) equipped with a voltage noninverted input terminal (In+), a current mode inverted input terminal (In-), and a loop filter which outputs a signal composed substantially of a triangular waveform and actualizes a single or plural gradient integrator, a cascade (C1) composed of a logic inverter or plural logic inverters which are coupled with the output terminal of the integrator and output logic PWM signals, an output power stage (P1) which converts the logic PWM signal to a PWM signal and switches between the potentials of two supply rails of the circuit, and a feedback resistance (Rf) which connects the output terminal of a power stage (P1) to the inverted input terminal (In-) of the operational amplifier (O1).

    2.
    发明专利
    未知

    公开(公告)号：DE69926728D1

    公开(公告)日：2005-09-22

    申请号：DE69926728

    申请日：1999-04-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASINI MARCO ,  TAVAZZANI CLAUDIO

    IPC: H03F3/217 ,  H03G11/00 ,  H03G11/04

    Abstract: A way of establishing a constant limit duty-cycle, substantially independent from fabrication process spread, temperature, etc., and to guarantee an optimal functioning of the final stage of the amplifier for all working conditions consists in detecting the equivalent values of the voltages to which the output signal of the amplifier switches (or pseudo supplies): VDD' and -VDD", respectively, and in making the limiting stage of the voltage swing of analog input signal utilize such pseudo supply values VDD' and -VDD" as respective reference values in limiting the voltage excursion of the analog signal VL output by the input limiting stage to a pre-defined fraction alpha

    5.
    发明专利
    未知

    公开(公告)号：DE69829852T2

    公开(公告)日：2006-03-02

    申请号：DE69829852

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

    IPC: H03F3/217

    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

    6.
    发明专利
    未知

    公开(公告)号：DE69926479D1

    公开(公告)日：2005-09-08

    申请号：DE69926479

    申请日：1999-04-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASINI MARCO ,  FRANCHINI LUIGI ,  LABBE ERIC

    IPC: H03F3/217

    Abstract: A class-D amplifier comprising an input integrating stage (Op-Amp, R1, C), a modulating stage (PWM) of the integrated input signal output by said integrating stage, using as a carrier an alternate waveform (Vtr) of a frequency (fsw), sufficiently higher than the frequency band of the analog input signal, outputting a digital signal switching between a positive voltage (+Vcc) and a negative voltage (-Vcc), and whose average value (Vo) represents an amplified replica of the input analog signal, an output power stage (BUFFER), producing an output digital signal (Vout), a feedback line constituted by a resistor (R2) connected between the output of said output power stage (BUFFER) and an input node of an operational amplifier (Op-Amp) constituting said integrating stage, and a low pass filter reconstructing an output analog signal (Vo), further comprises a delay stage (DELAY Td), functionally coupled in the direct path of propagation of said digital signal from the output of said PWM stage to an input of said output power stage (BUFFER), delaying said digital signal by a delay (Td) whose value is defined in function of a desired broadening of the bandwidth and in consideration of the corresponding restriction of the range of variation of the duty-cycle of the output digital signal.

    8.
    发明专利
    未知

    公开(公告)号：DE69926728T2

    公开(公告)日：2006-05-18

    申请号：DE69926728

    申请日：1999-04-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASINI MARCO ,  TAVAZZANI CLAUDIO

    IPC: H03F3/217 ,  H03G11/00 ,  H03G11/04

    Abstract: A way of establishing a constant limit duty-cycle, substantially independent from fabrication process spread, temperature, etc., and to guarantee an optimal functioning of the final stage of the amplifier for all working conditions consists in detecting the equivalent values of the voltages to which the output signal of the amplifier switches (or pseudo supplies): VDD' and -VDD", respectively, and in making the limiting stage of the voltage swing of analog input signal utilize such pseudo supply values VDD' and -VDD" as respective reference values in limiting the voltage excursion of the analog signal VL output by the input limiting stage to a pre-defined fraction alpha

    9.
    发明专利
    未知

    公开(公告)号：DE69829852D1

    公开(公告)日：2005-05-25

    申请号：DE69829852

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO ,  MASINI MARCO

    IPC: H03F3/217

    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

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