公开(公告)号：JPH07212156A

公开(公告)日：1995-08-11

申请号：JP23539794

申请日：1994-09-29

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI GIORGIO ,  MARCHIO FABIO ,  LUONI LIANA ,  COCETTA FRANCO

IPC: H03G11/00 ,  H03F1/52 ,  H03G11/02 ,  H03K17/082

Abstract: PURPOSE: To decrease a voltage across an equalization capacitor, to accelerate a charging process, and to make a current limiting action proper by providing an uni-directional current energizing circuit between one terminal the equalization capacitor and the gate of a power MOS transistor. CONSTITUTION: When a voltage across a resistor Rs is increased, and allowed to reach the voltage of a reference power source Vr, a transistor TRQ5 is turned off. Then, a TrQ4 turns on a TrQ6 to draw more current from the base of the TrQ6. Some portion of current Ig is thus allowed to flow to the emitter of the TrQ6, the gate voltage of a power MOSTrMp is decreased, and load current I is decreased. At this time, a equalization capacitor C is not sufficiently charged, and the TrQ4 draws current from the base of the TrQ6, and the gate of the TrMp continues to draw current from a current source Ig while the TrQ6 is turned off, and increases the load current I. When an unidirectional current energizing circuit 2 is arranged at a prescribed position, the equalization capacitor C can be charged at a higher rate. Also, an amplifier 1 is properly interposed, and the current I is limited at an output terminal F.

公开(公告)号：DE69322866D1

公开(公告)日：1999-02-11

申请号：DE69322866

申请日：1993-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI GIORGIO ,  MARCHIO FABIO ,  LUONI LIANA ,  COCETTA FRANCO

IPC: H03G11/00 ,  H03F1/52 ,  H03G11/02 ,  H03K17/082 ,  H03K17/08

Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load (Z) through a power Mos (Mp), being in particular of the regulated type using an equalizing capacitor (C). The addition of circuit means (2) with a one-way current flow between a terminal of said equalizing capacitor (C) and the gate terminal of (Mp) is effective to lower the voltage across the capacitor (C) and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuit means (2) may include a second Mos (M) of the same type as the power Mos (Mp). In this way, any deviations of (Mp) from its designed operation, as due to its manufacturing process and thermal drift phenomena, can be also compensated.

公开(公告)号：DE69322866T2

公开(公告)日：1999-05-20

申请号：DE69322866

申请日：1993-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROSSI GIORGIO ,  MARCHIO FABIO ,  LUONI LIANA ,  COCETTA FRANCO

IPC: H03G11/00 ,  H03F1/52 ,  H03G11/02 ,  H03K17/082 ,  H03K17/08

Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load (Z) through a power Mos (Mp), being in particular of the regulated type using an equalizing capacitor (C). The addition of circuit means (2) with a one-way current flow between a terminal of said equalizing capacitor (C) and the gate terminal of (Mp) is effective to lower the voltage across the capacitor (C) and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuit means (2) may include a second Mos (M) of the same type as the power Mos (Mp). In this way, any deviations of (Mp) from its designed operation, as due to its manufacturing process and thermal drift phenomena, can be also compensated.