LIMITER CIRCUIT
    1.
    发明专利

    公开(公告)号:JPH07212156A

    公开(公告)日:1995-08-11

    申请号:JP23539794

    申请日:1994-09-29

    Abstract: PURPOSE: To decrease a voltage across an equalization capacitor, to accelerate a charging process, and to make a current limiting action proper by providing an uni-directional current energizing circuit between one terminal the equalization capacitor and the gate of a power MOS transistor. CONSTITUTION: When a voltage across a resistor Rs is increased, and allowed to reach the voltage of a reference power source Vr, a transistor TRQ5 is turned off. Then, a TrQ4 turns on a TrQ6 to draw more current from the base of the TrQ6. Some portion of current Ig is thus allowed to flow to the emitter of the TrQ6, the gate voltage of a power MOSTrMp is decreased, and load current I is decreased. At this time, a equalization capacitor C is not sufficiently charged, and the TrQ4 draws current from the base of the TrQ6, and the gate of the TrMp continues to draw current from a current source Ig while the TrQ6 is turned off, and increases the load current I. When an unidirectional current energizing circuit 2 is arranged at a prescribed position, the equalization capacitor C can be charged at a higher rate. Also, an amplifier 1 is properly interposed, and the current I is limited at an output terminal F.

    3.
    发明专利
    未知

    公开(公告)号:DE69322866D1

    公开(公告)日:1999-02-11

    申请号:DE69322866

    申请日:1993-09-30

    Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load (Z) through a power Mos (Mp), being in particular of the regulated type using an equalizing capacitor (C). The addition of circuit means (2) with a one-way current flow between a terminal of said equalizing capacitor (C) and the gate terminal of (Mp) is effective to lower the voltage across the capacitor (C) and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuit means (2) may include a second Mos (M) of the same type as the power Mos (Mp). In this way, any deviations of (Mp) from its designed operation, as due to its manufacturing process and thermal drift phenomena, can be also compensated.

    4.
    发明专利
    未知

    公开(公告)号:DE69838973T2

    公开(公告)日:2009-01-02

    申请号:DE69838973

    申请日:1998-05-29

    Abstract: The tensioning apparatus is destined for use with silk screens essentially constituted by a flat frame (10) on which a screen material (2) or sieve is arranged. It comprises means for fixing the screen material (2) peripherally on the frame (10), and means for tensioning, associated to the frame (10), which operate between the frame (10) and the screen material (2) in order to tension the screen material (2).

    5.
    发明专利
    未知

    公开(公告)号:DE69322866T2

    公开(公告)日:1999-05-20

    申请号:DE69322866

    申请日:1993-09-30

    Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load (Z) through a power Mos (Mp), being in particular of the regulated type using an equalizing capacitor (C). The addition of circuit means (2) with a one-way current flow between a terminal of said equalizing capacitor (C) and the gate terminal of (Mp) is effective to lower the voltage across the capacitor (C) and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuit means (2) may include a second Mos (M) of the same type as the power Mos (Mp). In this way, any deviations of (Mp) from its designed operation, as due to its manufacturing process and thermal drift phenomena, can be also compensated.

    6.
    发明专利
    未知

    公开(公告)号:DE69838973D1

    公开(公告)日:2008-02-21

    申请号:DE69838973

    申请日:1998-05-29

    Abstract: The tensioning apparatus is destined for use with silk screens essentially constituted by a flat frame (10) on which a screen material (2) or sieve is arranged. It comprises means for fixing the screen material (2) peripherally on the frame (10), and means for tensioning, associated to the frame (10), which operate between the frame (10) and the screen material (2) in order to tension the screen material (2).

    7.
    发明专利
    未知

    公开(公告)号:DE69518977T2

    公开(公告)日:2001-03-22

    申请号:DE69518977

    申请日:1995-06-30

    Abstract: A reference voltage generator having a dual slope temperature characteristic, for use in an automotive alternator voltage regulator, comprises a bandgap circuit (R1,R2,R3,R4) which generates a voltage (A) having a thermal drift coefficient of zero and a voltage (B) having a non-zero thermal drift coefficient. These voltages are applied to a voltage divider (R5,R6) and a voltage-follower type of circuit (OPA1). A unidirectional conduction amplifier circuit (OPA2) has an input terminal connected to an intermediate point (C) on the voltage divider. A second voltage divider (R7,R8) is connected between the output terminals of the voltage-follower circuit (D) and the amplifier circuit (E). An intermediate node (F) of the second voltage divider is coupled to an output terminal (VREF) of the generator.

    8.
    发明专利
    未知

    公开(公告)号:DE69518977D1

    公开(公告)日:2000-11-02

    申请号:DE69518977

    申请日:1995-06-30

    Abstract: A reference voltage generator having a dual slope temperature characteristic, for use in an automotive alternator voltage regulator, comprises a bandgap circuit (R1,R2,R3,R4) which generates a voltage (A) having a thermal drift coefficient of zero and a voltage (B) having a non-zero thermal drift coefficient. These voltages are applied to a voltage divider (R5,R6) and a voltage-follower type of circuit (OPA1). A unidirectional conduction amplifier circuit (OPA2) has an input terminal connected to an intermediate point (C) on the voltage divider. A second voltage divider (R7,R8) is connected between the output terminals of the voltage-follower circuit (D) and the amplifier circuit (E). An intermediate node (F) of the second voltage divider is coupled to an output terminal (VREF) of the generator.

    9.
    发明专利
    未知

    公开(公告)号:DE60025904D1

    公开(公告)日:2006-04-20

    申请号:DE60025904

    申请日:2000-08-31

    Inventor: COCETTA FRANCO

    Abstract: The invention relates to a switching regulator circuit (10) producing a varying reference voltage (Vr) with temperature, which circuit includes a band-gap generator (2) for supplying at a power stage through an error amplifier (4) and a comparator (5). To the error amplifier (4) is also applied a regulated voltage (Vs) which may be produced by the regulator itself. Advantageously, the regulator (10) comprises a plurality of band-gap generators (12) being all supplied by the regulated voltage (Vs) and input a fraction of the regulated voltage (Vs) through a voltage divider (6), the respective outputs of the band-gap generators (12) being connected to a logic network (11) which has an output connected to the power stage. The error amplifier and comparator are incorporated to each of the generators (12).

    10.
    发明专利
    未知

    公开(公告)号:DE69718435T2

    公开(公告)日:2003-10-23

    申请号:DE69718435

    申请日:1997-02-07

    Abstract: The invention relates to a voltage regulator of the type comprising a linear filter (2), a comparator (3), and a stretcher filter (4) which are connected in cascade with one another between an input terminal (I1) and an output terminal (O1) of the regulator (1), the input terminal (I1) receiving an error signal (ERR) as converted by the comparator (3) into a square-wave error signal (ERRq), and the output terminal (O1) delivering a square-wave output control signal (Sout) which has a stretched duty cycle over the square-wave error signal (ERRq) by a time delay (tA) introduced from the stretcher filter (4). The regulator of this invention further comprises a non-linear filtering section (5) for the error signal (ERR) which is connected between the input terminal (I1) of the regulator (1) and the linear filter (2) and has linear gain with the error signal (ERR) below a first value (X1), gain approximately of unity with the error signal (ERR) between the first value (X1) and a second value (X2), and zero gain with the error signal (ERR) above the second value (X2). The invention also concerns a method for filtering a noisy electric signal.

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