IMPROVED DELAY LOCKED LOOP CIRCUIT

    公开(公告)号:JP2001168711A

    公开(公告)日:2001-06-22

    申请号:JP2000317034

    申请日:2000-10-17

    Abstract: PROBLEM TO BE SOLVED: To provide a delay locked loop circuit provided with a delay line provided with delay capable of being changed by a controlled method and a control circuit means for controlling the delay line so as to lock the delay line to a period T for delaying the periodic input signals of the period T. SOLUTION: The delay line 1 supplies plural delay cyclic signals CK1-CKN respectively delayed relating to the periodic input signals only for one part each of the delay. The control circuit means 2 and 7 are provided with a sequence detection circuit means 2 capable of periodically detecting the characteristic sequence of a digital value for indicating the delay by the delayed periodic signals and the delay Δt is reduced or increased so as to be locked to the period T corresponding to the type of the characteristic sequence.

    2.
    发明专利
    未知

    公开(公告)号:DE69929201D1

    公开(公告)日:2006-02-02

    申请号:DE69929201

    申请日:1999-10-18

    Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay ( DELTA t) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay ( DELTA t) to the period T. The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay ( DELTA t), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay ( DELTA t) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay ( DELTA t) for locking to the period T.

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