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公开(公告)号：JP2001177349A
公开(公告)日：2001-06-29
申请号：JP2000321411
申请日：2000-10-20
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI LUCIANO , GUINEA JESUS
IPC: H03K19/0944 , H03F1/30 , H03F3/30 , H03F3/343
Abstract: PROBLEM TO BE SOLVED: To obtain a circuit for compensating the difference between gate- source voltages of two MOS transistors of different types, caused by processing or a temperature change. SOLUTION: This circuit is provided characteristically with 1st and a 2nd transistors(TRs) Mp, Mn, 3rd and 4-th MOS TRs Mp1, Mn1 that are of the same type as that of the TRs Mp, Mn and formed in the same device, a means that biases the 3rd and 4-th Mp1, Mn1, a means consisting of Trs Mp4-Mp7 that measures a difference between the gate-source voltages of the 3rd and 4-th MOS TRs Mp1, Mn1, a means R1 that generates a compensation current I0 which is a function of the measured difference, and means S1-S3 and an Ro that use the compensation current I0 to change a bias of the 1st MOS TR Mp and the 2nd MOS TR Mn.
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公开(公告)号：JP2001168711A
公开(公告)日：2001-06-22
申请号：JP2000317034
申请日：2000-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , TOMASINI LUCIANO , MAGGIO SANTO
Abstract: PROBLEM TO BE SOLVED: To provide a delay locked loop circuit provided with a delay line provided with delay capable of being changed by a controlled method and a control circuit means for controlling the delay line so as to lock the delay line to a period T for delaying the periodic input signals of the period T. SOLUTION: The delay line 1 supplies plural delay cyclic signals CK1-CKN respectively delayed relating to the periodic input signals only for one part each of the delay. The control circuit means 2 and 7 are provided with a sequence detection circuit means 2 capable of periodically detecting the characteristic sequence of a digital value for indicating the delay by the delayed periodic signals and the delay Δt is reduced or increased so as to be locked to the period T corresponding to the type of the characteristic sequence.
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公开(公告)号：JP2001077798A
公开(公告)日：2001-03-23
申请号：JP2000238635
申请日：2000-08-07
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI LUCIANO , GUINEA JESUS
Abstract: PROBLEM TO BE SOLVED: To solve the problem of interference between two clock signals by providing a first circuit means for supplying a local timing signal and a second circuit means suitable for deciding a repeating timing signal which is selected in advance and which nearly synchronized with the first flow of digital data. SOLUTION: A synchronizing means is provided with a first circuit means (delay fixing loop circuit) 8 and a second circuit means 6. The circuit 8 is supplied with a local timing signal CK in order to generate a plurality of repeating timing signals CK1-CKn, which start from the signal CK and are mutually delayed by the fraction of one period. The means 6 is supplied with the first flow (RX, RXEQ) of digital data and supplied with the signals CK1-CKn to be suited to deciding a repeating timing signal CKR which is selected in advance and which nearly synchronizes with the first flow (RX, RXEQ) of the digital data in the plurality of timing signals.
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公开(公告)号：DE60025584D1
公开(公告)日：2006-04-06
申请号：DE60025584
申请日：2000-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , TOMASINI LUCIANO , MILANESE CARLO MARIA
Abstract: The present invention refers to a method and to an equalizer circuit of signals transmitted on a line. In an embodiment the equaliser circuit of signals transmitted on a line having an attenuation comprising: an analogical adaptive filter (1) applied in series to said line comprises at least two transconductance filters having a bias current (Pc1-Pcn) each and to which it is associated at least one pole and at least one zero the position in frequency of which in the working band (B) is variable in response to said bias current (Pc1-Pcn); a retroaction circuit (3, 4, 5, 6, 7) applied to the output of said filter (1) able to vary said bias current (Pc1-Pcn); said bias current (Pc1-Pcn) varies at the varying of said attenuation of said line; characterised in that said at least two transconductance filters have said bias current of prefixed value; said bias current is made to vary at the increasing of said attenuation so that said at least one pole is moved toward the high frequencies; said bias current is made to vary at the increasing of said attenuation so that said at least a zero is moved toward the low frequencies.
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公开(公告)号：DE69929201D1
公开(公告)日：2006-02-02
申请号：DE69929201
申请日：1999-10-18
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , TOMASINI LUCIANO , MAGGIO SANTO
Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay ( DELTA t) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay ( DELTA t) to the period T. The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay ( DELTA t), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay ( DELTA t) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay ( DELTA t) for locking to the period T.
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Patent Agency Ranking
公开(公告)号：ITMI20000064A1
公开(公告)日：2001-07-20
申请号：ITMI20000064
申请日：2000-01-20
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , MILANESE CARLO
Abstract: A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the "1" bits and "0" bits, sequence of bit present in the NRZ type binary signals.
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公开(公告)号：DE60123223D1
公开(公告)日：2006-11-02
申请号：DE60123223
申请日：2001-06-28
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , TOMASINI LUCIANO
IPC: H03L7/081
Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip - flop devices (37, ..., 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip - flop device (37, ..., 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27).
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公开(公告)号：DE69922811D1
公开(公告)日：2005-01-27
申请号：DE69922811
申请日：1999-10-21
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI LUCIANO , GUINEA JESUS
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公开(公告)号：IT1316285B1
公开(公告)日：2003-04-10
申请号：ITMI20000064
申请日：2000-01-20
Applicant: ST MICROELECTRONICS SRL
Inventor： GUINEA JESUS , MILANESE CARLO
Abstract: A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the "1" bits and "0" bits, sequence of bit present in the NRZ type binary signals.
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公开(公告)号：ITRM20000032D0
公开(公告)日：2000-01-20
申请号：ITRM20000032
申请日：2000-01-20
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI LUCIANO , GUINEA JESUS , CASTELLO RINALDO
Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.
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