公开(公告)号：JPH0690153A

公开(公告)日：1994-03-29

申请号：JP18449293

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

Abstract: PURPOSE: To switch an output node voltage by driving a capacitive load with a fast as well as low switching noise. CONSTITUTION: The gate voltage of a transistor Tr M5 is at low level, and the gate voltage of Trs M24 and M24B is at high level. An output shift period begins, when a signal CKO becomes low. A logical level of data from a memory cell is communicated to nodes C1 to 3. The node C1 turns on MX3 and turns off MX4. Since the node C2 keeps M20 on, a node G24 is maintained at a high level, the Trs M24 and M24B are turned off, and a pull-up branch does not contribute to the output current. As voltage of a node G5 increases, voltage that flows through branches M12 and M17 is reduced, voltage value is decreased, and the node 5 is charged by a current that decreases as a function of time. This realizes an output buffer which drives a capacitive load with a switching noise, and a voltage-switching method.

公开(公告)号：JPH06152335A

公开(公告)日：1994-05-31

申请号：JP11475493

申请日：1993-05-17

Applicant: ST MICROELECTRONICS SRL

Inventor： MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C17/00 ,  H03K3/03 ,  H03K3/354 ,  H03K5/151 ,  H03L7/24 ,  G11C16/06

Abstract: PURPOSE: To obtain a nonoverlapped phase signal generator which shows an improved nonoverlapped phase at the highest frequency without substantially shortening the operating-state time by incorporating two feedback gates which cross-couple two ring generators with each other. CONSTITUTION: When transmitters 01 and 02 normally operate, the voltage at a second connecting point 3 becomes lower and, therefore, a first coupling transistor MC is turned on, because the voltage at a first connecting point 2 becomes higher. When the voltage at another first connecting point 2A has not already become lower, in addition, the Voltage at another second connecting point 2A is made lower. A second coupling transistor MCA also has the same function. The waveforms of the voltages at the connecting points 2 and 2A and those of the voltages (indicating the output signals F1 and F of the transmitters 01 and 02) at connecting points 3 and 3A are maintained in opposite phases or, if not, are driven in desired opposite-phase states. Thus a nonoverlapping phase signal generator can generate two high-frequency signals having substantially nonoverlapping complementary waveforms.

公开(公告)号：DE69226627D1

公开(公告)日：1998-09-17

申请号：DE69226627

申请日：1992-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C17/00 ,  H03K3/03 ,  H03K3/354 ,  H03K5/151 ,  H03L7/24

Abstract: A non-overlapping phase, signal generator (1) comprises first and second loop oscillators (O1,O2) including cascaded inverters. Defined in each cascade of inverters are first and second circuit nodes between the inverters. Between the first node (2) of the first oscillator and the second node (3A) of the second oscillator, there is connected a transistor having a control terminal connected to the first node of the second oscillator. Connected between the first node (2A) of the second oscillator (O2) and the second node (3) of the first oscillator is a transistor having a control terminal connected to the first node of the first oscillator (O1).

公开(公告)号：DE69232170D1

公开(公告)日：2001-12-06

申请号：DE69232170

申请日：1992-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

公开(公告)号：DE69232170T2

公开(公告)日：2002-06-06

申请号：DE69232170

申请日：1992-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.