-
公开(公告)号：JPH08306190A
公开(公告)日：1996-11-22
申请号：JP22355395
申请日：1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , GASTALDI ROBERTO , ROLANDI PAOLO , TORELLI GUIDO
IPC: G11C11/419 , G11C7/06
Abstract: PROBLEM TO BE SOLVED: To obtain a readout circuit which is used for a memory having a differential cell, and which can be used even in memory reading by a reference cell technique and improves a data read speed and low voltage operations. SOLUTION: A readout circuit has two leg parts SX, DX which are connected to between power source terminals Vdd and Vss , and each of the leg parts series- connects an electronic switch SW1 or SW2; a passive element T1 or T2 forming a voltage amplifier which is feedback-connected to a passive element T2 or T1 in another leg part; and a switch load element L1 or L2 to each other. Each of the passive elements is driven via a high impedance circuit element D1 or D2.
-
公开(公告)号：JPH11260087A
公开(公告)日：1999-09-24
申请号：JP37435798
申请日：1998-12-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To alleviate a total load by providing a second and a third field effect transistors having the conductivity types same as or opposite to the first field effect transistor, providing a body connecting terminal to the first terminal thereof and then connecting the first terminal of the first transistor to the bias of the memory device. SOLUTION: A row driver includes a source terminal connected to a first drive voltage VBODY, a gate terminal connected to a bias voltage generator G1, a drain terminal connected to an input terminal IN of row driver and a PMOS transistor M1 having the body terminal connected to the source terminal. The row driver also includes a phase inverter I coupled between the input terminal IN and output terminal OUT. M1 is 'on' or 'off' depending on the voltage impressed to the node G1 in regard to the selected word line and M2 bomes 'on' while M3 becomes 'off' in the triode area.
-
3.发明专利
公开(公告)号：JPH0883493A
公开(公告)日：1996-03-26
申请号：JP23811794
申请日：1994-09-30
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , GASTALDI ROBERTO , MALCOVATI PIERO , TORELLI GUIDO
IPC: G11C17/00 , G11C5/14 , G11C16/06 , H01L21/822 , H01L27/04 , H02M3/07 , H03K19/0175
Abstract: PURPOSE: To obtain a voltage generation in a wide range and high reliability by a method wherein positive and negative voltages are generated by a voltage booster circuit and there are provided two 3-state logic gate circuits and additional 3-state logic gate circuit for operating a phase of a charge pump circuit incorporated in a booster. CONSTITUTION: Switch circuits (FFT1 to 6) comprise a 3-state logic gate circuit, boosters 7, 8 have command terminals ϕ1 , ϕ2 , a VDD terminal and a ground terminal, and when VDD is +5V, +10.5V and -10.5V. A booster 9 biases a substrate of a CMOS element of the booster 8. These are connected in a predetermined manner and gate capacitance C1 of a memory cell serves as a load. If a booster voltage is not acquired for the booster, an output is floated and the other boosters are nonactivated so as to occupy priority in common node control freely. With this structure, both positive and negative voltages for operating the memory cell via a control gate terminal are generated, an electrical load is operated, and selection in a wide IC technology and high reliability are obtained.
-
公开(公告)号：JP2000057787A
公开(公告)日：2000-02-25
申请号：JP6496099
申请日：1999-03-11
Applicant: ST MICROELECTRONICS SRL
Inventor： MALOBERTI FRANCO , ONETO ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To accurately perform programming by setting the component of a logic value to a value that correlates to the value of physical amount corresponding to the state of a memory cell, and by repeating a cycle until the logic value is completely determined. SOLUTION: The current supply capability of the transistor of a selected cell C12 is proportional to the difference between voltage on the gate terminal and the threshold voltage. Therefore, a current Icell being supplied by a selected cell C12 corresponds to a logic value being stored at the current Icell. The cell current Icell is supplied to the first input terminal of a comparison circuit SENS: 130, and another input terminal of the comparison circuit 130 receives various reference currents being generated by an appropriate circuit REF: 140. The circuit 130 is connected to an adjustment circuit COND: 120, compares the cell current Icell with a reference current Ir, generates a logic value LVcell at the output terminal, and corresponds to a data element being stored into a selected cell.
-
公开(公告)号：JPH06196944A
公开(公告)日：1994-07-15
申请号：JP16232693
申请日：1993-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： FLOCCHI CARLO , TORELLI GUIDO
Abstract: PURPOSE: To attain the output of programmable voltage in optimum state by providing a controlled current generator and an operational amplifier among a resistor element between two terminal of power source, serial circuit means and node to be linked with one side of power supply terminal and one side of resistor element. CONSTITUTION: The operational amplifier comprises a gain step AV and a source follower means connected to it (transistor MOUT biased by a constant current generator IB). In this case, a current iOUT of transistor MOUT is supplied to a load every time because of output branch bias current IB and made equal with the current of bit line selective transistor. The current iOUT is reflected on a constant current generator G1 and passed through two dummy transistors MWd' and MBd' and a voltage drop VBL generated at bit line selecting transistors MW and MB is compensated. The contribution from a bias current IB to a current iS to be injected into dummy transistors MWd' and MBd' is started from the contribution to a voltage value VREF despite of current value supplied to the load by a voltage regulator.
-
Patent Agency Ranking
公开(公告)号：JPH06152335A
公开(公告)日：1994-05-31
申请号：JP11475493
申请日：1993-05-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MARCHESI GIANMARCO , TORELLI GUIDO
Abstract: PURPOSE: To obtain a nonoverlapped phase signal generator which shows an improved nonoverlapped phase at the highest frequency without substantially shortening the operating-state time by incorporating two feedback gates which cross-couple two ring generators with each other. CONSTITUTION: When transmitters 01 and 02 normally operate, the voltage at a second connecting point 3 becomes lower and, therefore, a first coupling transistor MC is turned on, because the voltage at a first connecting point 2 becomes higher. When the voltage at another first connecting point 2A has not already become lower, in addition, the Voltage at another second connecting point 2A is made lower. A second coupling transistor MCA also has the same function. The waveforms of the voltages at the connecting points 2 and 2A and those of the voltages (indicating the output signals F1 and F of the transmitters 01 and 02) at connecting points 3 and 3A are maintained in opposite phases or, if not, are driven in desired opposite-phase states. Thus a nonoverlapping phase signal generator can generate two high-frequency signals having substantially nonoverlapping complementary waveforms.
-
公开(公告)号：JP2002319293A
公开(公告)日：2002-10-31
申请号：JP2002107937
申请日：2002-04-10
Applicant: ST MICROELECTRONICS SRL
Inventor： GREGORI STEFANO , MICHELONI RINO , PIERIN ANDREA , KHOURI OSAMA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To realize a method for speedily and highly precisely programming a memory cell. SOLUTION: In the method for programming a non-volatile memory cell 1, at least first and second programming pulse trains F1, F2 having pulse width increasing in stages are applied continuously to a control terminal 2 of the memory cell 1, but amplitude increment between a pulse in the first programming train F1 and the next one is made larger than the amplitude increment between a pulse in the second programming train F2 and the next one. Advantageously, third programming pulse trains F0, F3, having pulse width which increases in stages, are applied to the control terminal 2 of the memory cell 1 before the first programming pulse train F1, but amplitude increment between a pulse and the next one is made smaller than the amplitude increment in the first programming train F1, and is substantially equal to the amplitude increment in the second programming train F2 or larger than the amplitude increment in the first programming train F1.
-
公开(公告)号：JP2001057091A
公开(公告)日：2001-02-27
申请号：JP2000236205
申请日：2000-08-03
Applicant: ST MICROELECTRONICS SRL
Inventor： TORELLI GUIDO , MODELLI ALBERTO , MANSTRETTA ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To obtain aprogramming method for a non-volatile memory in which the time required for performing programming operation can be minimized by control of gate voltage. SOLUTION: Threshold voltage in which a value is increased for a pre- programming pulse at the time of programming is applied to a gate terminal of each cell to be programmed, and an increment of threshold voltage of a cell to be programmed is made equal to an increment of gate voltage (ΔVcp). Variation interval of threshold voltage relating to each level is held at a small value to move from one threshold level to a next threshold level, in order to reduce a whole programming time, continuous pulses are supplied to each cell to be programmed with non-verifying until it is reduced to a voltage level to be programmed or less (107-109), and a verifying process (110) is performed, successively, a programming process and a verifying process (112, 110, 117, 118) are continuously performed until a cell to be programmed reaches the desired threshold value.
-
公开(公告)号：JP2001042955A
公开(公告)日：2001-02-16
申请号：JP2000199353
申请日：2000-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , MICHELONI RINO , MOTTA ILARIA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To obtain a stable voltage adjusting circuit simple in configuration. SOLUTION: This circuit is equipped with voltage dividers R1 and R2 which are connected between 1st and 2nd output terminals VDD of a source voltage generator and GND, have input terminals IN and output terminals OUT, and are connected between an output node connected to the output terminals OUT and 2nd terminals GND and an operational amplifier OP which has an inverted input terminal connected to the input terminals, an uninverted input terminal connected to an intermediate node of the voltage dividers, and an output terminal for driving a 1st field effect transistor MPU between the output node and 1st terminals; and the output terminal of the operational amplifier is connected to the output node through a compensating network COMP, and a 2nd field effect transistor MPD which is connected between the output node and the 2nd terminals and has a control terminal is provided and has its gate terminal connected to a constant-voltage generating circuit.
-
10.发明专利
公开(公告)号：JP2000067592A
公开(公告)日：2000-03-03
申请号：JP14849699
申请日：1999-05-27
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To provide a selector switch, integrated monolithically for a device containing an electrically programmable memory cell, which has a simple circuit and operation capability adapted to various use. SOLUTION: Selector switches are integrated monolithically in a circuit of CMOS technology for a memory cell device being electrically programmable and having at least first and second input terminals connecting with first (HV) and second (LV) voltage generators respectively and an output terminal (OUT). First (P1) and second (P2) field effect selection transistors are connected between the first input terminal and the output terminal and the second input terminal and the output terminal respectively through a first and second terminal.
-
-
-
-
-
-
-
-
-
Search Results
76
records
(took 0.025 seconds)
