公开(公告)号：JPH0690153A

公开(公告)日：1994-03-29

申请号：JP18449293

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

Abstract: PURPOSE: To switch an output node voltage by driving a capacitive load with a fast as well as low switching noise. CONSTITUTION: The gate voltage of a transistor Tr M5 is at low level, and the gate voltage of Trs M24 and M24B is at high level. An output shift period begins, when a signal CKO becomes low. A logical level of data from a memory cell is communicated to nodes C1 to 3. The node C1 turns on MX3 and turns off MX4. Since the node C2 keeps M20 on, a node G24 is maintained at a high level, the Trs M24 and M24B are turned off, and a pull-up branch does not contribute to the output current. As voltage of a node G5 increases, voltage that flows through branches M12 and M17 is reduced, voltage value is decreased, and the node 5 is charged by a current that decreases as a function of time. This realizes an output buffer which drives a capacitive load with a switching noise, and a voltage-switching method.

公开(公告)号：JP2000057787A

公开(公告)日：2000-02-25

申请号：JP6496099

申请日：1999-03-11

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  ONETO ANDREA ,  TORELLI GUIDO

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To accurately perform programming by setting the component of a logic value to a value that correlates to the value of physical amount corresponding to the state of a memory cell, and by repeating a cycle until the logic value is completely determined. SOLUTION: The current supply capability of the transistor of a selected cell C12 is proportional to the difference between voltage on the gate terminal and the threshold voltage. Therefore, a current Icell being supplied by a selected cell C12 corresponds to a logic value being stored at the current Icell. The cell current Icell is supplied to the first input terminal of a comparison circuit SENS: 130, and another input terminal of the comparison circuit 130 receives various reference currents being generated by an appropriate circuit REF: 140. The circuit 130 is connected to an adjustment circuit COND: 120, compares the cell current Icell with a reference current Ir, generates a logic value LVcell at the output terminal, and corresponds to a data element being stored into a selected cell.

公开(公告)号：DE69232170D1

公开(公告)日：2001-12-06

申请号：DE69232170

申请日：1992-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

公开(公告)号：DE69827601D1

公开(公告)日：2004-12-23

申请号：DE69827601

申请日：1998-03-27

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  ONETO ANDREA ,  TORELLI GUIDO

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/26 ,  G11C11/00

Abstract: Method (200) for reading a multiple-level memory cell (C12) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), comprising the steps of setting (210) an actual physical quantity (Is1) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C12), and repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C12), a cycle (215-235) comprising the steps of setting (227, 232) a component of the logical value (Di) to a value which is a function of a range in which the actual physical quantity (Isi) lies, determined by comparing (215, 220) the actual physical quantity (Isi) with at least one reference physical quantity (Iri) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Isi), and setting (237) the actual physical quantity for a possible next cycle (Is(i+1)) to a relative value of the actual physical quantity (Isi) with respect to the range in which it lies.

公开(公告)号：DE69232170T2

公开(公告)日：2002-06-06

申请号：DE69232170

申请日：1992-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

公开(公告)号：IT201800002464A1

公开(公告)日：2019-08-07

申请号：IT201800002464

申请日：2018-02-07

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTI EDOARDO ,  SALIMATH ARUNKUMAR ,  BONIZZONI EDOARDO ,  MALOBERTI FRANCO ,  CACCIAGRANO PAOLO ,  BRAMBILLA DAVIDE LUIGI

IPC: H03F20060101