公开(公告)号：DE69915251D1

公开(公告)日：2004-04-08

申请号：DE69915251

申请日：1999-03-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO ,  NAGARI ANGELO ,  MECCHIA ALESSANDRO

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).

公开(公告)号：IT201700031177A1

公开(公告)日：2018-09-21

申请号：IT201700031177

申请日：2017-03-21

Applicant: ST MICROELECTRONICS SRL

Inventor： QUARTIROLI MATTEO ,  MECCHIA ALESSANDRO ,  PESENTI PAOLO ,  FACCHINETTI STEFANO ,  DONADEL ANDREA

IPC: H04L27/36 ,  G01C19/5776 ,  H04L27/38

公开(公告)号：IT201700031167A1

公开(公告)日：2018-09-21

申请号：IT201700031167

申请日：2017-03-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MECCHIA ALESSANDRO ,  QUARTIROLI MATTEO ,  PESENTI PAOLO

IPC: H04L27/36 ,  G01C19/5776 ,  H04L27/38