公开(公告)号：JP2001135100A

公开(公告)日：2001-05-18

申请号：JP2000272586

申请日：2000-09-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory device in which complete test of a word line can be performed with a low cost. SOLUTION: The non-volatile memory device integrates a memory cell array 2, a voltage generating circuit REG supplying operation voltage Vr to be adjusted to a ward line LWL1, and short circuit detecting circuit 10 in the same chip 100. The short circuit detecting circuit 10 detects output current IM1 of the voltage generating circuit REG for biasing a cell 3 of the selected word line LWL1. The output current IM1 is made a first value IM1' when short circuit is not caused, and it is made a second value IM1" when short circuit is caused between the selected word line LWL1 and adjacent word lines LWL0- LWLn. The short circuit detecting circuit 10 compares output current IM1 of the voltage generating circuit REG with the reference value Iref, and generates a short circuit digital signal Vo indicating whether short circuit is caused at an output or not.

公开(公告)号：DE69937559D1

公开(公告)日：2007-12-27

申请号：DE69937559

申请日：1999-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G11C29/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

公开(公告)号：DE69937559T2

公开(公告)日：2008-10-23

申请号：DE69937559

申请日：1999-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G11C29/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.