公开(公告)号：JP2001135100A

公开(公告)日：2001-05-18

申请号：JP2000272586

申请日：2000-09-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory device in which complete test of a word line can be performed with a low cost. SOLUTION: The non-volatile memory device integrates a memory cell array 2, a voltage generating circuit REG supplying operation voltage Vr to be adjusted to a ward line LWL1, and short circuit detecting circuit 10 in the same chip 100. The short circuit detecting circuit 10 detects output current IM1 of the voltage generating circuit REG for biasing a cell 3 of the selected word line LWL1. The output current IM1 is made a first value IM1' when short circuit is not caused, and it is made a second value IM1" when short circuit is caused between the selected word line LWL1 and adjacent word lines LWL0- LWLn. The short circuit detecting circuit 10 compares output current IM1 of the voltage generating circuit REG with the reference value Iref, and generates a short circuit digital signal Vo indicating whether short circuit is caused at an output or not.

公开(公告)号：JP2001057097A

公开(公告)日：2001-02-27

申请号：JP2000227650

申请日：2000-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10

Abstract: PROBLEM TO BE SOLVED: To obtain a single power voltage type non-volatile storage device having a hierarchical column decoder in which the bias time of a word line at the level of staircase voltage can be shortened. SOLUTION: This storage device 10 has a memory cell array 2 having structure of a form provided with global word lines 4 and local word lines 6, a global column decoding means 8 for addressing the global word lines 4, a local column decoding means 12 for addressing the local word lines 6, a global power supply means 22 for supplying power to the global column decoding means 8, and a local power supply means 24 for supplying power to a local column decoding means 12.

公开(公告)号：IT1319075B1

公开(公告)日：2003-09-23

申请号：ITMI20002367

申请日：2000-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA

IPC: G11C16/10 ,  G11C16/24

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

公开(公告)号：IT1320666B1

公开(公告)日：2003-12-10

申请号：ITTO20000892

申请日：2000-09-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  MICHELONI RINO ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

公开(公告)号：IT1306963B1

公开(公告)日：2001-10-11

申请号：ITMI990080

申请日：1999-01-19

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  MOTTA ILARIA ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30

公开(公告)号：ITTO990994A1

公开(公告)日：2001-05-16

申请号：ITTO990994

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

公开(公告)号：DE69937559D1

公开(公告)日：2007-12-27

申请号：DE69937559

申请日：1999-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G11C29/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

公开(公告)号：ITTO20000892A1

公开(公告)日：2002-03-22

申请号：ITTO20000892

申请日：2000-09-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

公开(公告)号：IT1311441B1

公开(公告)日：2002-03-12

申请号：ITTO990994

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

公开(公告)号：IT1311440B1

公开(公告)日：2002-03-12

申请号：ITTO990993

申请日：1999-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

IPC: G11C11/56 ,  G11C16/30

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.