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    1.
    发明专利
    未知

    公开(公告)号：DE60133021D1

    公开(公告)日：2008-04-10

    申请号：DE60133021

    申请日：2001-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： POLIZZI SALVATORE ,  PERRONI MAURIZIO

    IPC: G11C16/26 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

    Abstract: A memory device includes a standard memory core, an input buffer receiving an external clock signal and producing an internal clock signal, an output path of data read from the standard memory core comprising a state machine receiving the internal clock signal for controlling the data stream coupled to the output of the standard memory through a first internal data bus, and an output buffer coupled to the output of the state machine through a second internal bus and comprising an output stage enabled by the state machine for producing the read data on an output bus. The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal, said array receiving data from the state machine through the second internal bus and providing the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slaves flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device comprises a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

    5.
    发明专利
    未知

    公开(公告)号：ITVA20020012A1

    公开(公告)日：2003-08-08

    申请号：ITVA20020012

    申请日：2002-02-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PERRONI MAURIZIO ,  POLIZZI SALVATORE

    IPC: G11C7/10

    Abstract: A memory device includes an internal address bus, and first and second internal data busses. A memory receives from the internal address bus an address of memory data to be read, and transfers read memory data in blocks of N bits to the first internal data bus. An address storing circuit is coupled to the internal address bus for storing the address of the memory data to be read. An array of latches is coupled to the first internal data bus for storing the read memory data received therefrom. The array of latches includes two banks of latches. Each bank has N latches and is controlled independently from the other bank by respective commands, and each bank stores bits present on the first internal data bus upon receiving the respective commands. The second internal data bus is also connected to the array of latches. A state machine is connected to the array of latches for providing the respective commands for control thereof, and the state machine alternates the respective commands for commanding a consecutive reading of the blocks of N bits.

    7.
    发明专利
    未知

    公开(公告)号：ITVA20010035A1

    公开(公告)日：2003-04-16

    申请号：ITVA20010035

    申请日：2001-10-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PERRONI MAURIZIO ,  POLIZZI SALVATORE ,  POLI SALVATORE

    IPC: G11C7/10 ,  G11C16/08 ,  G11C16/26

    Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

    10.
    发明专利
    未知

    公开(公告)号：ITVA20020012D0

    公开(公告)日：2002-02-08

    申请号：ITVA20020012

    申请日：2002-02-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PERRONI MAURIZIO ,  POLIZZI SALVATORE

    IPC: G11C7/10

    Abstract: A memory device includes an internal address bus, and first and second internal data busses. A memory receives from the internal address bus an address of memory data to be read, and transfers read memory data in blocks of N bits to the first internal data bus. An address storing circuit is coupled to the internal address bus for storing the address of the memory data to be read. An array of latches is coupled to the first internal data bus for storing the read memory data received therefrom. The array of latches includes two banks of latches. Each bank has N latches and is controlled independently from the other bank by respective commands, and each bank stores bits present on the first internal data bus upon receiving the respective commands. The second internal data bus is also connected to the array of latches. A state machine is connected to the array of latches for providing the respective commands for control thereof, and the state machine alternates the respective commands for commanding a consecutive reading of the blocks of N bits.

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