公开(公告)号：DE60214868D1

公开(公告)日：2006-11-02

申请号：DE60214868

申请日：2002-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  GIAMBARTINO ANTONIO ,  LA MALFA ANTONINO ,  POLIZZI SALVATORE

IPC: G11C16/10 ,  G11C16/12

Abstract: The invention relates to a circuit architecture and a method for performing a page programming in non volatile memory electronic devices equipped with a memory cell matrix (3) and an SPI serial communication interface (2), as well as circuit portions associated to the cell matrix (3) and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank (5) is provided to store and draw data during the page programming in the pseudo-serial mode through said interface (2). Data latching is performed one bit at a time and the following data retrieval occurs instead with at least two bytes at a time.

公开(公告)号：DE102015121512B4

公开(公告)日：2021-06-02

申请号：DE102015121512

申请日：2015-12-10

Applicant: ST MICROELECTRONICS SRL

Inventor： QUARTIROLI MATTEO ,  POLI SALVATORE ,  TRIPOLI GIOVANNI CARLO ,  FARAVELLI ROBERTO

IPC: H03M1/38 ,  H03M1/14 ,  H03M1/46

Abstract: Verfahren für Analog/Digital-Wandlung mindestens eines ersten Signals (X, Y, Z) und mindestens eines zweiten Signals (T), wobei das mindestens eine zweite Signal im Vergleich zu dem mindestens einen ersten Signal (X, Y, Z) ein langsam variierendes Signal mit schmaler Bandbreite ist, wobei das Verfahren folgende Schritte beinhaltet:- Abtasten (14) des mindestens einen ersten Signals (X, Y, Z) und des mindestens einen zweiten Signals (T) zur Erzeugung von Abtastungen davon für Analog/Digital-Wandlung,- Unterziehen der Abtastungen des mindestens einen ersten Signals (X, Y, Z) einer Digitalwandlung mit einer bestimmten Wandlungsrate (ADC1),- Unterziehen der Abtastungen des mindestens einen zweiten Signals (T) einer Digitalwandlung in Segmenten (T1, T2, T3), wobei die Segmente einer Digitalwandlung zusammen mit den Abtastungen des mindestens einen ersten Signals (X, Y, Z) mit der bestimmten Wandlungsrate (ADC1) unterzogen werden, und- Rekonstruieren von digitalgewandelten Abtastungen des mindestens einen zweiten Signals (T) von den einer Digitalwandlung unterzogenen Segmenten (T1, T2, T3).

公开(公告)号：ITVA20020016A1

公开(公告)日：2003-08-21

申请号：ITVA20020016

申请日：2002-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

IPC: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

公开(公告)号：DE102015121512A1

公开(公告)日：2016-06-23

申请号：DE102015121512

申请日：2015-12-10

Applicant: ST MICROELECTRONICS SRL

Inventor： QUARTIROLI MATTEO ,  POLI SALVATORE ,  TRIPOLI GIOVANNI CARLO ,  FARAVELLI ROBERTO

IPC: H03M1/38 ,  H03M1/46

Abstract: Eines oder mehrere erste Signale (X, Y, Z) und eines oder mehrere zweite Signale (T), wobei das (die) zweite(n) Signal(e) im Vergleich zu den ersten Signalen (X, Y, Z) ein langsam variierende(s) Schmalbandsignal(e) ist (sind), werden analog/digital gewandelt durch: – Abtasten des(r) ersten Signals(e), um Abtastungen davon für Analog/Digital-Wandlung zu erzeugen, – Unterziehen der Abtastungen des(r) ersten Signals(e) Digitalwandlung bei einer bestimmten Wandlungsrate (ADC1), – Unterziehen der Abtastungen des zweiten Signals (T) Digitalwandlung in Segmenten (T1, T2, T3), so dass diese Segmente zusammen mit den Abtastungen des(r) ersten Signals(e) Digitalwandlung mit der entsprechenden Wandlungsrate (ADC1) unterzogen werden, und – Rekonstruieren von digitalgewandelten Abtastungen des zweiten Signals (T) aus den Digitalwandlung unterzogenen Segmenten (T1, T2, T3).

公开(公告)号：ITMI20021185A1

公开(公告)日：2003-12-01

申请号：ITMI20021185

申请日：2002-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  PERRONI MAURIZIO ,  POLI SALVATORE

IPC: G11C11/16 ,  G11C16/32 ,  G11C29/14

公开(公告)号：ITVA20020016D0

公开(公告)日：2002-02-21

申请号：ITVA20020016

申请日：2002-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

IPC: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

公开(公告)号：ITMI20021583A1

公开(公告)日：2004-01-19

申请号：ITMI20021583

申请日：2002-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  LA MALFA ANTONINO

IPC: G06F12/00 ,  G06F12/06 ,  G11C8/06 ,  G11C15/00

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

公开(公告)号：ITVA20010035A1

公开(公告)日：2003-04-16

申请号：ITVA20010035

申请日：2001-10-16

Applicant: ST MICROELECTRONICS SRL

Inventor： PERRONI MAURIZIO ,  POLIZZI SALVATORE ,  POLI SALVATORE

IPC: G11C7/10 ,  G11C16/08 ,  G11C16/26

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

公开(公告)号：ITMI20021185D0

公开(公告)日：2002-05-31

申请号：ITMI20021185

申请日：2002-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  PERRONI MAURIZIO ,  POLI SALVATORE

IPC: G11C11/16 ,  G11C16/32 ,  G11C29/14