公开(公告)号：JP2001313374A

公开(公告)日：2001-11-09

申请号：JP2001095119

申请日：2001-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PESCHIAROLI DANIELA ,  MAURELLI ALFONSO ,  PALUMBO ELISABETTA ,  PIAZZA FAUSTO

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for integrating a nonvolatile memory and a high performance logic circuit network in the same semiconductor chip. SOLUTION: The floating gate of a memory cell of a nonvolatile memory and a gate electrode of a high voltage transistor regarding the nonvolatile memory are formed of a first polysilicon layer, and the control gate of a memory cell of the nonvolatile memory and the gate electrode of a low voltage transistor regarding a high performance logic circuit network are formed of a second polysilicon layer.