公开(公告)号：JP2001313374A

公开(公告)日：2001-11-09

申请号：JP2001095119

申请日：2001-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PESCHIAROLI DANIELA ,  MAURELLI ALFONSO ,  PALUMBO ELISABETTA ,  PIAZZA FAUSTO

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for integrating a nonvolatile memory and a high performance logic circuit network in the same semiconductor chip. SOLUTION: The floating gate of a memory cell of a nonvolatile memory and a gate electrode of a high voltage transistor regarding the nonvolatile memory are formed of a first polysilicon layer, and the control gate of a memory cell of the nonvolatile memory and the gate electrode of a low voltage transistor regarding a high performance logic circuit network are formed of a second polysilicon layer.

公开(公告)号：DE60326351D1

公开(公告)日：2009-04-09

申请号：DE60326351

申请日：2003-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  MAURELLI ALFONSO ,  PESCHIAROLI DANIELA ,  ZABBERONI PAOLA

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/105

Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),forming a second conductive layer (11) on a second portion of semiconductor substrate (1),defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).