公开(公告)号：JP2001313374A

公开(公告)日：2001-11-09

申请号：JP2001095119

申请日：2001-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PESCHIAROLI DANIELA ,  MAURELLI ALFONSO ,  PALUMBO ELISABETTA ,  PIAZZA FAUSTO

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for integrating a nonvolatile memory and a high performance logic circuit network in the same semiconductor chip. SOLUTION: The floating gate of a memory cell of a nonvolatile memory and a gate electrode of a high voltage transistor regarding the nonvolatile memory are formed of a first polysilicon layer, and the control gate of a memory cell of the nonvolatile memory and the gate electrode of a low voltage transistor regarding a high performance logic circuit network are formed of a second polysilicon layer.

公开(公告)号：JP2000164835A

公开(公告)日：2000-06-16

申请号：JP33420599

申请日：1999-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  MAURELLI ALFONSO

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a process that can easily integrate a nonvolatile memory and a high-performance logic circuit on the same chip. SOLUTION: A method for manufacturing integrated circuit includes the steps of forming first gate oxide layers of first transistors on first sections of a substrate 1, a step of forming a second gate oxide layer 5 of memory cells on second sections of the substrate 1, and a step of forming gate electrodes 8 of the first transistors and floating gate electrodes 7 of the memory cells of first polysilicon layers 6 in the first and second gate oxide layers 3 and 5. The method also includes a step of forming dielectric layers o the floating gate electrodes 7, a step of forming third gate oxide layers 24 of second transistors on third sections of the substrate 1, a step of forming control gate electrodes of the memory cells and the gate electrodes of the second transistor of second polysilicon layers on the dielectric layers and third sections of the substrate 1, and a step of forming the source and drain regions of the first transistors on the first sections of the substrate 1. In addition to these steps, the method also includes a step of forming source and drain regions of memory cells on the second sections of the substrate 1 and a step of forming the source and drain region of the second transistors on the third sections of the substrate 1.

公开(公告)号：JPH04359477A

公开(公告)日：1992-12-11

申请号：JP18255591

申请日：1991-07-23

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a single polysilicon level EPROM cell comprising a partially superposed floating gate on a double dope source and a drain region, requiring no additional mask, within a process range for obtaining an LDD or DDD type transistor. CONSTITUTION: With regions 7, 8, and 9 of P-type semiconductor substrate N type implanted at the same time, a control gate 9, a high dope source region 7, and a drain region 8 are formed to constitute a channel region 4. After oxide growth (11), (12), sticking and formation are performed with a polysilicon layer 10, and a region 1 constitutes a floating gate which, while formed on the control gate 9 and the channel region 4, is partially superposed on the source region 7 and the drain region 8.

公开(公告)号：JP2000057789A

公开(公告)日：2000-02-25

申请号：JP15223299

申请日：1999-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MAURELLI ALFONSO

IPC: G11C16/06 ,  G11C7/06 ,  G11C16/28

Abstract: PROBLEM TO BE SOLVED: To reduce the complexity in the design and control of a reference cell by comparing charge states with each other, and by generating a two-bit signal for coding the charge states by the output. SOLUTION: In the case of both erased memory cells, even when cells F1 and F2 adsorb different current, mirroring is made in first and second current mirror circuits 19, 20, 33, and 34, and voltages 01 and 02 are set to a high level for corresponding to a logic state '11'. In the written cells F1 and F2, the cells do not adsorb current, and current being mirrored in first and second current mirror circuits 19, 20, 22, and 23 is insufficient to reduce the voltage in I/O nodes 41a and 41b. The output voltages 01 and 02 correspond to a logic state '00'. In the case of the cells F1 and F2 being similarly erased and written, respectively, and in the case of the cells F1 and F2 being written and erased, respectively, the each logic state is set to '10' or '01'.

公开(公告)号：JP2000124335A

公开(公告)日：2000-04-28

申请号：JP28933699

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a low-cost OTP memory. SOLUTION: In manufacturing an integrated semiconductor device, having at least a nonvolatile floating gate memory cell 20 and at least a logic transistor 10 between a step of selectively etching and moving a dielectric layer 7 on a region for forming the logic transistor 10 and a first polysilicon layer 3 and a step of depositing a second polysilicon layer 11, a first substep of removing a first gate oxide layer 2 at the logic transistor 10 region and a second substep of growing a second gate oxide layer 9 on this region are provided, so as to make the second gate oxide layer 9 different from the first gate oxide layer 2.

公开(公告)号：JPH11260097A

公开(公告)日：1999-09-24

申请号：JP36334998

申请日：1998-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO ,  MAURELLI ALFONSO ,  OLIVO MARCO

IPC: G11C16/06 ,  G06F11/10 ,  G11C29/00 ,  G11C29/06 ,  G11C29/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for self-testing and correcting an error caused by the charge loss of a flash memory. SOLUTION: Read and parity check are repeated sequentially per byte and integrity is verified for values stored in respective parity bits of a parity value. It the verification is negative, and parity verification is continued sequentially starting from the first row until a row generating a negative verification result is identified while sustaining the current row address. If a discrete tail bit is '1', it is rewritten to '0'.

公开(公告)号：JPH07106604A

公开(公告)日：1995-04-21

申请号：JP20366994

申请日：1994-08-29

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: PURPOSE: To manufacture an integrated voltage control/stabilizing element having stable clamp voltage without additionally providing a manufacturing process in a flash EEPROM memory device. CONSTITUTION: This manufacturing method contains a process with which an N-type low doped well 2 is formed in a single crystal silicon substrate 1, a process with which an active region 4 is formed on the surface of the N-type well 2, a process with which a thin gate oxide layer is grown on the active region 4, and a process with which an N-type region 6 is formed by implanting the first high dosage of N-type dopant into the N-type well 2. Also, a process with which an N contact region 7 is obtained against both of the N-type well 2 and the N-type region 6 by implanting the N-type dopant of the second high dose higher than the first high dose, and a process with which a P region 8 is formed by implanting the P-type dopant of the third high dose, which is higher than the first high dose, into the N-type region 6, are provided.

公开(公告)号：DE60326351D1

公开(公告)日：2009-04-09

申请号：DE60326351

申请日：2003-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  MAURELLI ALFONSO ,  PESCHIAROLI DANIELA ,  ZABBERONI PAOLA

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/105

Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),forming a second conductive layer (11) on a second portion of semiconductor substrate (1),defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).

公开(公告)号：DE69820594D1

公开(公告)日：2004-01-29

申请号：DE69820594

申请日：1998-05-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MAURELLI ALFONSO

IPC: G11C16/06 ,  G11C7/06 ,  G11C16/28

Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

公开(公告)号：DE69032937T2

公开(公告)日：1999-06-17

申请号：DE69032937

申请日：1990-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  G11C16/04

Abstract: The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).