公开(公告)号：ITMI20001567D0

公开(公告)日：2000-07-11

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：IT1318145B1

公开(公告)日：2003-07-23

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BEZ ROBERTO ,  CAMERLENGHI EMILIO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：ITMI20001567A1

公开(公告)日：2002-01-11

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).