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    MINUTE CONTACT AREA IN SEMICONDUCTOR DEVICE, HIGH PERFORMANCE PHASE CHANGE MEMORY CELL AND METHOD OF MANUFACTURING THE MEMORY CELL
    1.
    发明专利
    MINUTE CONTACT AREA IN SEMICONDUCTOR DEVICE, HIGH PERFORMANCE PHASE CHANGE MEMORY CELL AND METHOD OF MANUFACTURING THE MEMORY CELL 有权

    公开(公告)号：JP2003174144A

    公开(公告)日：2003-06-20

    申请号：JP2002353352

    申请日：2002-12-05

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： BEZ ROBERTO ,  PELLIZZER FABIO ,  RIVA CATERINA ,  ZONCA ROMINA

    IPC: H01L27/10 ,  G11C16/02 ,  H01L27/105 ,  H01L27/24 ,  H01L45/00

    Abstract: PROBLEM TO BE SOLVED: To provide a high performance phase change memory cell of the minute contact structure. SOLUTION: The contact structure comprises a first conductive area having a first thin film portion of a first sublithographic size in a first direction, and a second conductive area having a second thin film portion of a second sublithographic size in a second direction crossing the first direction. The first and second thin film portions are electrically in contact with each other to form a contact surface including the sublithographic extending area. The thin film portions are formed with a deposition method in place of the lithography method. The first thin film portion is deposited to the wall of an aperture within a first dielectric material layer. The second thin film portion may be formed by depositing a sacrifice area to the perpendicular wall of a first limit layer, depositing a second limit layer to the side surface where the sacrifice area is not deposited, removing thereafter the sacrifice area, forming a sublithographic aperture for etching the mold aperture in the mold layer, and then filling the mold aperture. COPYRIGHT: (C)2003,JPO

    2.
    发明专利
    未知

    公开(公告)号：DE60331629D1

    公开(公告)日：2010-04-22

    申请号：DE60331629

    申请日：2003-01-15

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  BEZ ROBERTO ,  TOSI MARINA

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/24

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    3.
    发明专利
    未知

    公开(公告)号：DE60327527D1

    公开(公告)日：2009-06-18

    申请号：DE60327527

    申请日：2003-09-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLIZZER FABIO ,  DE SANDRE GUIDO ,  BEZ ROBERTO

    IPC: H03K19/177 ,  G11C16/02 ,  G11C16/04 ,  H03K3/037

    Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (1151-1152,1151-1153), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    4.
    发明专利
    未知

    公开(公告)号：DE602005009793D1

    公开(公告)日：2008-10-30

    申请号：DE602005009793

    申请日：2005-01-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZULIANI PAOLA ,  PELLIZZER FABIO ,  BEZ ROBERTO

    IPC: H01L27/24

    Abstract: Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

    5.
    发明专利
    未知

    公开(公告)号：DE60217120T2

    公开(公告)日：2007-10-25

    申请号：DE60217120

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  BEZ ROBERTO

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: The cell array includes number of N-type base regions (12) which are provided overlying a P-type common collector region (11) in a body (10). P-type emitter regions (14) and N-type base contact regions (15) are formed in the base regions such that the base contact regions have a doping level higher than the doping level of the base regions and each base regions is shared by at least two bipolar transistors (20). An independent claim is also included for a cell array manufacturing process.

    6.
    发明专利
    未知

    公开(公告)号：DE60310915D1

    公开(公告)日：2007-02-15

    申请号：DE60310915

    申请日：2003-08-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLIZZER FABIO ,  BEZ ROBERTO

    IPC: H01L27/24

    Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).

    7.
    发明专利
    未知

    公开(公告)号：DE60214496D1

    公开(公告)日：2006-10-19

    申请号：DE60214496

    申请日：2002-09-27

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： CASAGRANDE GIULIO ,  LOWREY TYLER ,  BEZ ROBERTO ,  WICKER GUY ,  SPALL EDWARD ,  HUDGENS STEPHEN ,  CZUBATYJ WOLODYMYR

    IPC: G11C11/34 ,  G11C11/56 ,  G11C16/02

    Abstract: A memory device (100) including a plurality of memory cells (Mh,k), a plurality of insulated first regions (220h) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230k) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (Dh,k) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225h) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (Dh,k,Dh,k+1) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    9.
    发明专利
    未知

    公开(公告)号：ITMI20001567D0

    公开(公告)日：2000-07-11

    申请号：ITMI20001567

    申请日：2000-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

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