-
公开(公告)号：JP2733030B2
公开(公告)日：1998-03-30
申请号：JP32565494
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERLENGHI EMILIO , CASAGRANDE GIULIO
-
2.发明专利Method for reforming effect of esd protection of semiconductor circuit structure, and circuit structure thereof 审中-公开用于改善半导体电路结构的ESD保护效果的方法及其电路结构
公开(公告)号：JPH11274166A
公开(公告)日：1999-10-08
申请号：JP37004798
申请日：1998-12-25
Inventor： COLOMBO PAOLO , CAMERLENGHI EMILIO
IPC: H01L29/73 , H01L21/331 , H01L27/02 , H01L29/732 , H01L29/735
CPC classification number: H01L29/735 , H01L27/0259
Abstract: PROBLEM TO BE SOLVED: To improve the ESD protection of an electronic element.
SOLUTION: This method and circuit structure is for reforming the effect of protection of an ESD in circuit structure made in a semiconductor substrate, covered with the epitaxial layer 3 which is equipped with at least one ESD protecting lateral bipolar transistor 5 formed at the surface of the epitaxial layer 3, and a circuit structure so as to form a well 4 which is isolated from a substrate 2 under the transistor 5. The bipolar transistor 5 is completely isolated from the substrate 2 by first (10) and second (11) n-type wells which extend downward from the epitaxial layer 3 to the embedded well 4 and in contact with it.
COPYRIGHT: (C)1999,JPOAbstract translation: 要解决的问题：改善电子元件的ESD保护。 解决方案：该方法和电路结构用于重整在半导体衬底中形成的电路结构中ESD保护的效果，该半导体衬底被外延层3覆盖，外延层3配备有至少一个ESD保护侧面双极晶体管5， 外延层3和电路结构，以形成与晶体管5下面的衬底2隔离的阱4.双极晶体管5通过第一（10）和第二（11）n与衬底2完全隔离 型阱，其从外延层3向下延伸到嵌入阱4并与其接触。
-
公开(公告)号：JP2733029B2
公开(公告)日：1998-03-30
申请号：JP32565394
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor： CASAGRANDE GIULIO , CAMERLENGHI EMILIO
-
公开(公告)号：JPH07220491A
公开(公告)日：1995-08-18
申请号：JP32565494
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERLENGHI EMILIO , CASAGRANDE GIULIO
Abstract: PURPOSE: To make a programming line voltage the function of the actual length of a memory cell by incorporating a circuit element to a voltage adjuster. CONSTITUTION: The voltage adjuster 3 is provided with a gain stage, which is provided with an input terminal connected to the voltage divider 6 of a programming voltage VPP and an output terminal U connected with he programming line 5 of at least one memory cell 2 and supplied with programming voltage VPP. In addition at least one circuit element capable of suiting a programming line voltage to the length of the memory cell 2 is provided. The circuit element is the voltage divider 6 of the programming voltage VPP and is provided with variable resistance values R1 to R3.
-
公开(公告)号：JPH0883500A
公开(公告)日：1996-03-26
申请号：JP14503495
申请日：1995-06-12
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , CAMERLENGHI EMILIO
Abstract: PURPOSE: To obtain a memory device endurable in a gain reduction. CONSTITUTION: Column and/or row address decode means RDEC, CDEC comprise at least one address mapping nonvolatile memory NVM. A read and write control logic part CL comprises identifying means TST designed so as to identify a cell fail in a column and/or a row of a matrix MAT of a memory device; and means WM for writing an address corresponding to a column and/or a row RID existing in the matrix MAT on the nonvolatile memory NVM during normal operations, and cell characteristics can readily and effectively be decided.
-
Patent Agency Ranking
公开(公告)号：JPH07220490A
公开(公告)日：1995-08-18
申请号：JP32565394
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor： CASAGRANDE GIULIO , CAMERLENGHI EMILIO
Abstract: PURPOSE: To make the voltage drop of a circuit element the function of the actual length of a memory cell by incorporating the circuit element to a voltage adjuster. CONSTITUTION: The voltage adjuster 3 is provided with a gain stage, which is provided with an input terminal connected to the voltage divider 6 of a programming voltage VPP and an output terminal U connected with the programming line 5 of at least one memory cell 2 and supplied with programming voltage VPP. In addition at least one circuit element 4 compensating the fluctuation of a percentage by a programming line voltage for the length of the memory cell 2 is provided.
-
7.发明授权Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate 有权用于提高在半导体衬底中形成的电路结构中的ESD保护的有效性的方法和电路公开(公告)号：US6372597B2
公开(公告)日：2002-04-16
申请号：US83713701
申请日：2001-04-17
Applicant: ST MICROELECTRONICS SRL
Inventor： COLOMBO PAOLO , CAMERLENGHI EMILIO
IPC: H01L29/73 , H01L21/331 , H01L27/02 , H01L29/732 , H01L29/735
CPC classification number: H01L29/735 , H01L27/0259
Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.
Abstract translation: 描述了一种方法和相关的电路结构，用于提高在覆盖有外延层的半导体衬底中实现的电路结构中的ESD保护的有效性，并且包括在外延层的表面中实现的至少一个ESD保护横向双极晶体管。 该方法包括在晶体管下形成将晶体管与衬底隔离的隔离阱。 有利的是，晶体管可以通过第一和第二N阱从衬底完全隔离，该N阱从外延层的表面向下延伸到埋入阱并与其接触。
-
公开(公告)号：DE60205344D1
公开(公告)日：2005-09-08
申请号：DE60205344
申请日：2002-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERLENGHI EMILIO , CAPPELLETTI PAOLO , GHILARDI TECLA , SALI MAURO , SERVALLI GIORGIO
-
公开(公告)号：DE60326351D1
公开(公告)日：2009-04-09
申请号：DE60326351
申请日：2003-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMERLENGHI EMILIO , MAURELLI ALFONSO , PESCHIAROLI DANIELA , ZABBERONI PAOLA
IPC: H01L21/8247 , H01L21/8234 , H01L23/31 , H01L27/105
Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),forming a second conductive layer (11) on a second portion of semiconductor substrate (1),defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).
-
公开(公告)号：DE69325278T2
公开(公告)日：1999-11-11
申请号：DE69325278
申请日：1993-12-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CASAGRANDE GIULIO , CAMERLENGHI EMILIO
Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.022 seconds)
