公开(公告)号：DE69637095D1

公开(公告)日：2007-07-05

申请号：DE69637095

申请日：1996-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  COLABELLA ELIO ,  PIVIDORI LUCA ,  REBORA ADRIANA SGS-THOMSON

IPC: H01L21/8247 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions made up of a first conducting layer (4), an intermediate dielectric layer (5) and a second conducting layer (6) with said regions being insulated from each other by insulation regions (7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer (11,12), of the second conducting layer (6) and of the intermediate dielectric layer (5) respectively, and a following isotropic etching of the first conducting layer (4).