公开(公告)号：JP2000200844A

公开(公告)日：2000-07-18

申请号：JP37471499

申请日：1999-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： FONTANA GABRIELLA ,  PIVIDORI LUCA

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To prevent a silicide film from being formed on a doped region inside a semiconductor substrate. SOLUTION: A step is provided, where a dielectric film 6 is formed so as to cover all regions which require a silicification treatment before a silicifying step is carried out, and a polysilicon part 5 is not covered with the dielectric film 6. A region on the left polysilicon part 5 is subjected to a preferable silicification treatment without introducing an additional masking step.

公开(公告)号：DE602004025197D1

公开(公告)日：2010-03-11

申请号：DE602004025197

申请日：2004-02-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PIVIDORI LUCA

IPC: H01L27/105 ,  H01L21/8247

Abstract: The invention relates to a method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area in a process for manufacturing semiconductor integrated non volatile memory devices, wherein an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the array and circuitry areas. A thin stack comprising at least a thin dielectric layer (7) and a third conductive layer (9) is provided over a second conductive layer (6) before the step of defining the control gate structures in the array and the single gates in the circuitry. This intermediate stack of multiple layers is used in order to compensate for the thickness differences, between the dual gate structures in the array and the single gate transistors in the circuitry.

公开(公告)号：DE69633242D1

公开(公告)日：2004-09-30

申请号：DE69633242

申请日：1996-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： COLABELLA ELIO ,  PIVIDORI LUCA ,  REBORA ADRIANA

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：ITMI991130A1

公开(公告)日：2000-11-21

申请号：ITMI991130

申请日：1999-05-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PIVIDORI LUCA ,  BRUSAFERRI LIDIA

IPC: H01L21/8247 ,  H01L27/105

Abstract: A method of fabricating non-volatile memory devices integrated in a semiconductor substrate is presented. The memory devices include a matrix of non-volatile memory cells, each having floating-gate MOS transistors with associated gate electrodes, as well as control circuitry formed of MOS transistors also having gate electrodes. The method includes forming gate electrodes above the substrate, then depositing a first dielectric layer onto the entire exposed surface. Next the first dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the matrix cells. Then a second dielectric layer is deposited onto the entire exposed surface, and the memory matrix is overlaid with a protective layer. In the circuitry area, the second dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors, while the floating-gate MOS transistors are protected.

公开(公告)号：DE69637095D1

公开(公告)日：2007-07-05

申请号：DE69637095

申请日：1996-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  COLABELLA ELIO ,  PIVIDORI LUCA ,  REBORA ADRIANA SGS-THOMSON

IPC: H01L21/8247 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions made up of a first conducting layer (4), an intermediate dielectric layer (5) and a second conducting layer (6) with said regions being insulated from each other by insulation regions (7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer (11,12), of the second conducting layer (6) and of the intermediate dielectric layer (5) respectively, and a following isotropic etching of the first conducting layer (4).

公开(公告)号：DE69832083D1

公开(公告)日：2005-12-01

申请号：DE69832083

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： FONTANA GABRIELLA ,  PIVIDORI LUCA

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

Abstract: A selective silicidation process for electronic devices (1) integrated on a semiconductor substrate (2), said devices (1) comprising a plurality of active elements (3) formed with gate regions (4) which comprise at least one polysilicon layer (5), comprises the following steps: depositing a dielectric layer (6) over the entire surface of the semiconductor; removing said dielectric layer (6) to expose the polysilicon layer (5) of said gate regions (4); depositing a layer of a transition metal (7); subjecting the transition metal layer to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer (8) over said gate regions (4).

公开(公告)号：ITMI20042372A1

公开(公告)日：2005-03-14

申请号：ITMI20042372

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PIVIDORI LUCA