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    CONTROLLABLE FREQUENCY OSCILLATOR
    1.
    发明专利
    CONTROLLABLE FREQUENCY OSCILLATOR 失效

    公开(公告)号：JPH1174765A

    公开(公告)日：1999-03-16

    申请号：JP17473498

    申请日：1998-06-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CELANT LUCA ,  DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  RIGAZIO LUCA

    IPC: H03K3/0231 ,  H03K3/282

    Abstract: PROBLEM TO BE SOLVED: To operate with power supply voltage that is lower than normal power supply voltage by configuring a connection circuit means with a differential amplifier which has a differential output terminal that is connected to the bases of two transistors respectively. SOLUTION: A balanced differential amplifier is provided between two transistors Q1 and Q2 as a connecting means for positive feedback. The differential amplifier has two npn transistors T3 and T4, interconnects their emitters, also connects its current Ip to a ground terminal through a current source G5 which is adjusted by the voltage of a control terminal SW, connects their collectors to a power supply terminal Vcc through respectively different resistance R3 and R4 and connects their bases to the collectors of the transistors Q2 and Q1 respectively. The collectors of the transistors T3 and T4 are further connected to bases of the transistors Q2 and Q1 respectively and also each collector can be taken out as an output terminal Vout of this oscillator.

    INTEGRATED CIRCUIT
    2.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH1186459A

    公开(公告)日：1999-03-30

    申请号：JP19573198

    申请日：1998-07-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CELANT LUCA ,  DE MICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  RIGAZIO LUCA

    IPC: G11B20/14 ,  H03B29/00 ,  H03L7/07 ,  H03L7/22

    Abstract: PROBLEM TO BE SOLVED: To prevent locking caused by injection of two oscillators due to stray current in an integrated circuit. SOLUTION: The integrated circuit has two phase lock groups, R-PLL, W-PLL, and each of these phase lock groups has its own oscillators OSC-1, OSC-2. The oscillator OSC-2 of one of these phase lock groups, W-PLL, is coupled with a noise generator N-GEN. And a means TM which operates this noise generator N-GEN is installed so that injected noise randomly changes the frequency of the oscillator OSC-2 of the above one phase lock group when the other phase lock group is in operation.

    3.
    发明专利
    未知

    公开(公告)号：DE69632304D1

    公开(公告)日：2004-06-03

    申请号：DE69632304

    申请日：1996-02-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIGAZIO LUCA

    IPC: H03K3/356

    Abstract: The circuit (300) is for translating a switching signal (Ldrive) disposed between the earth level (0V) and Vdd to a translated switching signal (hdrive) disposed between Vhsrc and Vhstrap. The circuit (300) comprises a bistable circuit formed by two branches which include two nMOS transistors (315, 320) the sources of which are connected to earth and which are controlled, respectively, by a switching-on signal (on) and by a switching-off signal (off) derived from the switching signal (Ldrive) by means of a buffer (305) and an inverter (310), respectively. Two pMOS transistors (325, 330) having their sources at the voltage Vhstrap and the drain of one connected to the gate of the other output the translated switching signal (hdrive) at one of their drains. Two further pMOS transistors (335, 340) having gates at the voltage Vhsrc are interposed between the two nMOS transistors (315, 320) and the two pMOS transistors (325, 330).

    4.
    发明专利
    未知

    公开(公告)号：DE69431205D1

    公开(公告)日：2002-09-26

    申请号：DE69431205

    申请日：1994-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SANDRI PAOLO ,  BORGHI MARIA ROSA ,  RIGAZIO LUCA

    IPC: H02M3/156 ,  H02M3/00

    Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.

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