公开(公告)号：JP2001229691A

公开(公告)日：2001-08-24

申请号：JP2000374346

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  MICHELONI RINO ,  PIERIN ANDREA ,  YERO EMILIO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory device having row redundancy being freely constituted in which correcting capability of architecture can be reconstituted for each chip. SOLUTION: This device comprises a row decoding circuit 12 and a column decoding circuit 13, a circuit reading out stored data in a memory cell and changing it, a memory matrix 14 which can store a fault row address, and a control circuit. The device also comprises a circuit comparing a fault row address stored in the memory matrix 14 with a selected row address in order to recognize a selected row address ADr and perform relieving selection of a fault row and selection of a corresponding redundant cell row at the time of recognizing validness, and configuration register comprising a matrix of a non-volatile memory cell and a control circuit.

公开(公告)号：DE60020210D1

公开(公告)日：2005-06-23

申请号：DE60020210

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  MICHELONI RINO ,  PIERIN ANDREA ,  YERO EMILIO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

公开(公告)号：DE60015916D1

公开(公告)日：2004-12-23

申请号：DE60015916

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI STEFANO ,  FERRARIO DONATO ,  YERO EMILIO ,  CAMPARDO GIOVANNI

IPC: H03K19/177

Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row. An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.