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    ROW DECODING CIRCUIT FOR ELECTRONIC MEMORY DEVICE AND METHOD OF CONTROLLING ROW DECODING STEP
    2.
    发明专利
    ROW DECODING CIRCUIT FOR ELECTRONIC MEMORY DEVICE AND METHOD OF CONTROLLING ROW DECODING STEP 失效

    公开(公告)号：JPH11260083A

    公开(公告)日：1999-09-24

    申请号：JP37435898

    申请日：1998-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  FERRARIO DONATO ,  GHEZZI STEFANO

    IPC: G11C16/06 ,  G11C8/08 ,  G11C11/408

    Abstract: PROBLEM TO BE SOLVED: To enable accurate operation in different conditions by providing a cascade-connected inverter of a hierarchical structure, a circuit for dynamically increasing step by step a read voltage level, a first means for increasing a read voltage level to a particular voltage and a second means for increasing a read voltage level to the other particular voltage. SOLUTION: A first means increases a read voltage level to a value equal to the supply voltage + threshold voltage and a second means increases a read voltage level to a value equal to the supply voltage +2 × threshold voltage. A memory row is selected by simultaneously setting the pre-decoding signals LX, LY, LZ and P to high logical values to form a first decoding final inverter 15 provided with the transistors M9 and M10. The voltage supplied to the designated rows of address is boosted to Vcc+2Vtp. In the rows not designated, the voltage Vcc+Vtp is transferred to the center node Xc of the transistors M9 and M10.

    4.
    发明专利
    未知

    公开(公告)号：DE69636161D1

    公开(公告)日：2006-06-29

    申请号：DE69636161

    申请日：1996-07-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  GHEZZI STEFANO ,  GOLLA CARLA MARIA

    IPC: H01L29/94

    Abstract: A MOS capacitor comprises a semiconductor substrate (2), a first well region (1;8) of a first conductivity type formed in the substrate, at least one doped region (4;11) formed in the first well region, and an insulated gate layer (5,6) insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.

    6.
    发明专利
    未知

    公开(公告)号：DE69831728D1

    公开(公告)日：2006-02-09

    申请号：DE69831728

    申请日：1998-04-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  BRANCHETTI MAURIZIO ,  GHEZZI STEFANO

    IPC: G05F3/20 ,  H01L27/115

    Abstract: The invention relates to an integrated structure (1) for memory cells formed over a semiconductor substrate (2) doped with a first dopant type and including at least one memory cell (CM) in turn formed in a conductive well (3) provided in said semiconductor substrate (2) and doped with a second dopant type, said conductive well (3) having an additional well (4) formed therein which is doped with the first dopant type and comprises active areas (5,6) of the memory cell (CM). According to the invention, a substrate bias terminal (8), formed in the additional well (4), is further associated with the memory cell (CM) to receive a suitable bias voltage (Vpol) to lower the threshold voltage (Vth) of the memory cell (CM) by body effect. The invention also relates to a biasing device (13) for a memory cell (CM) which has at least one substrate bias terminal (8) associated therewith, the biasing device comprising at least a first sub-threshold circuitry block (A) adapted to supply an appropriate current during the device standby phase through a restore transistor (M1) connected between a supply voltage reference (Vcc) and the substrate bias terminal (8) of the memory cell (CM), and having a control terminal connected to a bias circuit (14), in turn connected between the supply voltage reference (Vcc) and a ground voltage reference (GND) to drive the restore transistor (M1) with a current of limited value. The device according to the invention further comprises a second feedback block (B) for fast charging the substrate bias terminal (8), being connected between the supply voltage reference (Vcc) and the ground voltage reference (GND) and comprising a first bias transistor (M2) having a control terminal connected to the ground voltage reference (GND) via a stabilization transistor (M3), having in turn a control terminal connected to an output node (OC), and to the control terminal of a first regulation transistor (M4) connected between the supply voltage reference (Vcc) and the ground voltage reference (GND), the stabilization transistor (M3) and first regulation transistor (M4) providing feedback for the bias transistor (M2), thereby to restrict the voltage range of the output node (OC).

    8.
    发明专利
    未知

    公开(公告)号：DE60015916D1

    公开(公告)日：2004-12-23

    申请号：DE60015916

    申请日：2000-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHEZZI STEFANO ,  FERRARIO DONATO ,  YERO EMILIO ,  CAMPARDO GIOVANNI

    IPC: H03K19/177

    Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row. An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.

    9.
    发明专利
    未知

    公开(公告)号：DE69634509D1

    公开(公告)日：2005-04-28

    申请号：DE69634509

    申请日：1996-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  GHEZZI STEFANO ,  BRANCHETTI MAURIZIO

    IPC: H03K17/22

    Abstract: The present invention relates to an electronic power on reset circuit (1) of the type comprising a comparator (2) having at least two inputs and one output (A) for receiving a first reference signal from a generator block (11) and a second signal proportional to a supply voltage (Vdd) from a divider block (12) and for producing at output an initialization signal (INTPOR). Advantageously the output (A) is connected to a third turn off enablement input (10) of the comparator (2) through the series of an inverter pair (I1,I2). The generator block (11) and the divider block (12) also comprise respective turn off enablement inputs (15,13) connected downstream of the inverter pair (I1,I2).

    10.
    发明专利
    未知

    公开(公告)号：ITMI20031126D0

    公开(公告)日：2003-06-05

    申请号：ITMI20031126

    申请日：2003-06-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHEZZI STEFANO ,  IACULO MASSIMO ,  GUIDA NICOLA ,  POLLIO ANTONINO ,  DELLAMONICA ANGELO ,  BAGGI PIETRO

    IPC: G06F12/02 ,  G06F12/08

    Abstract: The mass memory device includes a flash memory (205) having a plurality of physical sectors, suitable to be erased individually, each one including a plurality of physical blocks and a method for emulating a random-access logical memory space having a plurality of logical sectors each one including a plurality of logical blocks, the logical sectors being grouped into at least one group. The method includes partitioning a random-access logical memory space into a plurality of logical sectors each one including a plurality of logical blocks, the logical sectors being grouped into at least one group of logical sectors; associating a corresponding data physical sector with each of the logical sectors and associating a plurality of corresponding buffer physical sectors with each group of logical sectors; setting at least one of the buffer physical sectors as an active buffer physical sector; writing each of the logical blocks into one of an available physical block of the corresponding data physical sector if the corresponding data physical sector is not full; and the corresponding active buffer physical sector if the corresponding data physical sector is full; setting another buffer physical sector as active, in response to the active buffer physical sector becoming full; and defragging each data physical sector which is full and associated with a logical sector having at least one logical block stored in the corresponding buffer physical sector which is full.

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