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    2.
    发明专利
    未知

    公开(公告)号：DE69718435T2

    公开(公告)日：2003-10-23

    申请号：DE69718435

    申请日：1997-02-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAFARANA ALESSANDRO ,  COCETTA FRANCO ,  MERLO MAURO

    IPC: H02M3/156 ,  H02P9/30 ,  H03K5/08

    Abstract: The invention relates to a voltage regulator of the type comprising a linear filter (2), a comparator (3), and a stretcher filter (4) which are connected in cascade with one another between an input terminal (I1) and an output terminal (O1) of the regulator (1), the input terminal (I1) receiving an error signal (ERR) as converted by the comparator (3) into a square-wave error signal (ERRq), and the output terminal (O1) delivering a square-wave output control signal (Sout) which has a stretched duty cycle over the square-wave error signal (ERRq) by a time delay (tA) introduced from the stretcher filter (4). The regulator of this invention further comprises a non-linear filtering section (5) for the error signal (ERR) which is connected between the input terminal (I1) of the regulator (1) and the linear filter (2) and has linear gain with the error signal (ERR) below a first value (X1), gain approximately of unity with the error signal (ERR) between the first value (X1) and a second value (X2), and zero gain with the error signal (ERR) above the second value (X2). The invention also concerns a method for filtering a noisy electric signal.

    3.
    发明专利
    未知

    公开(公告)号：DE69718435D1

    公开(公告)日：2003-02-20

    申请号：DE69718435

    申请日：1997-02-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAFARANA ALESSANDRO ,  COCETTA FRANCO ,  MERLO MAURO

    IPC: H02M3/156 ,  H02P9/30 ,  H03K5/08

    Abstract: The invention relates to a voltage regulator of the type comprising a linear filter (2), a comparator (3), and a stretcher filter (4) which are connected in cascade with one another between an input terminal (I1) and an output terminal (O1) of the regulator (1), the input terminal (I1) receiving an error signal (ERR) as converted by the comparator (3) into a square-wave error signal (ERRq), and the output terminal (O1) delivering a square-wave output control signal (Sout) which has a stretched duty cycle over the square-wave error signal (ERRq) by a time delay (tA) introduced from the stretcher filter (4). The regulator of this invention further comprises a non-linear filtering section (5) for the error signal (ERR) which is connected between the input terminal (I1) of the regulator (1) and the linear filter (2) and has linear gain with the error signal (ERR) below a first value (X1), gain approximately of unity with the error signal (ERR) between the first value (X1) and a second value (X2), and zero gain with the error signal (ERR) above the second value (X2). The invention also concerns a method for filtering a noisy electric signal.

    4.
    发明专利
    未知

    公开(公告)号：ITMI20002042D0

    公开(公告)日：2000-09-19

    申请号：ITMI20002042

    申请日：2000-09-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAFARANA ALESSANDRO ,  CASTELLI CLAUDIA

    IPC: H02M3/158

    Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

    10.
    发明专利
    未知

    公开(公告)号：ITMI20002233A1

    公开(公告)日：2002-04-16

    申请号：ITMI20002233

    申请日：2000-10-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAFARANA ALESSANDRO ,  CASTELLI CLAUDIA

    IPC: G06F1/26

    Abstract: A managing system manages a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, the VRMs having output terminals connected together and arranged to communicate over a common bus. The managing system includes an error amplifier being input an output voltage signal from the VRM plurality, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from the VRM plurality and being connected to the common bus. The error amplifier effects a comparison of the input signals to generate a control voltage signal to the VRM plurality. Advantageously, the managing system comprises a controller connected to the equivalent droop resistor.

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