公开(公告)号：JPH0864811A

公开(公告)日：1996-03-08

申请号：JP19326495

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

公开(公告)号：JPH0897168A

公开(公告)日：1996-04-12

申请号：JP16869395

申请日：1995-07-04

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of highly integrated MOS power device. SOLUTION: Insulating gate layers 8 and insulating layers 11 are formed on a semiconductor layer 2, next to a plurality of slender windows having long edges 17 and short edges sectioning respectively exposed surface fine strips 16 are formed by selectively removing layers 8 and 11. Then the slender windows are implanted with a first dopant vertically thereto and perpendicularly to the layer 2 so as to be symmetrically tilted at the surface of the layer 2 making an angle. These angles depending upon the gross thickness of the layers 8 and 11 for preventing the first dopant from being implanted into the central fine strips of the fine strips 16 to form the pairs of source regions 6 extending along the edges 17 of respective windows, also separated by the central fine strips further symmetrically tilted making another angle to be implanted with a second dopant to form respective regions with two channel regions 5, extending to the under side of the long edges of respective windows finally implanted with a third dopant to form the regions aligned with the edges 17 of the windows using the layers 11 as masks.

公开(公告)号：JPH0846200A

公开(公告)日：1996-02-16

申请号：JP17871495

申请日：1995-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an MOS technology power device having integrated circuit in which the series resistance of gate can be decreased without increasing the number of gate metal finger parts. SOLUTION: The MOS technology power device of integrated structure comprises a plurality of functional units of basic component formed in a lightly doped first conductivity type semiconductor layer 1 wherein the functional unit has a second conductivity type channel region 6 coated with a conductive insulation gate layer 8 including a polysilicon layer 5. The conductive insulation gate layer 8 has resistivity significantly lower than that of the polysilicon layer 5 superposed by a highly conductive layer 9. Since a resistance introduced by the polysilicon layer 5 is shunted by a resistance introduced by the highly conductive layer 9, total resistivity of the conductive insulation gate layer 8 is decreased.

公开(公告)号：JPH08213614A

公开(公告)日：1996-08-20

申请号：JP19759695

申请日：1995-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a parasitic resistance value and inductance of wire and pin by separating units comprising a plurality of function units with such a region of a semiconductor layer as no function unit is formed. SOLUTION: A semiconductor material layer 5 is selectively coated with an insulated gate layer 11 extending on a first doped region 7, and the gate layer 11 is made to contact gate metal meshes 101 and 102 connected to at least one gate metal pad, while surrounding a source metal plate 100. By connecting the gate metal pad to each pin P8 of a package with each bonding wire W8, all MOSFET units among all the MOSEFT units are connected in parallel. Thus, the maximum current capacity of the power device can be re- established, while each source electrode pin can be electrically speared according to individual purposes, resulting in significantly improved freedom in design.

公开(公告)号：JPH0817848A

公开(公告)日：1996-01-19

申请号：JP15598295

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

Abstract: PURPOSE: To ignore the base series resistance of a parasitic perpendicular bipolar transistor by adjusting an ion implantation energy so that the peak of the dopant concentration of a heavily doped part of a body region is located on the lower side of a source region than the surface of a semiconductor layer. CONSTITUTION: With an insulation gate layer 10 on the surface of a semiconductor layer 3 as a mask, a first impurity is ion-implanted with an energy in a specific thickness from the surface of the semiconductor layer 3 and is thermally diffused, thus forming a body region 2 consisting of a first greatly doped part 5 that is nearly aligned to both edges of the insulation layer 10 and a horizontal diffusion part 6 at the lower side of the insulation layer 10. The second impurity is ion-implanted selectively into the body region 2 in a pair, thus forming an annular source 7 that is aligned to both edges of the insulation layer 10, thus forming the greatly doped part 5 of the first impurity so that it is located at the lower side of the annular source region 7 and ignoring the base series resistance of a parasitic perpendicular bipolar transistor.

公开(公告)号：JP2618615B2

公开(公告)日：1997-06-11

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

公开(公告)号：JPH0817849A

公开(公告)日：1996-01-19

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: PURPOSE: To reduce the manufacturing process of the channel region of a basic function unit and to reduce the ON resistance of a power device by forming the deep body part and the channel part of a body region only by ion implantation without performing any thermal diffusion treatment. CONSTITUTION: After a first dopant is selectively ion-implanted into a heavily doped part 5 in a direction that orthogonally crosses a semiconductor surface with a proper amount of dosage and an energy of ion implantation with an insulation gate layer 8 as a mask, a second dopant is selectively ion-implanted into a region 6 along a direction that is inclined at a prescribed angle in an orthogonally crossed direction, thus forming a body region 2. Then, a large dosage of third dopant is ion-implanted into the greatly doped part 5 to form a source region 7 that is nearly aligned to the edge part of the insulation gate layer 8, thus reducing the manufacturing process of the channel region of a basic function unit since no thermal diffusion treatment is made and reducing the on resistance of a power device.

公开(公告)号：DE69518653D1

公开(公告)日：2000-10-05

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69418037D1

公开(公告)日：1999-05-27

申请号：DE69418037

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

公开(公告)号：DE69434937D1

公开(公告)日：2007-04-19

申请号：DE69434937

申请日：1994-06-23

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8).