公开(公告)号：DE69518653T2

公开(公告)日：2001-04-19

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69518653D1

公开(公告)日：2000-10-05

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：JPH0653510A

公开(公告)日：1994-02-25

申请号：JP15092991

申请日：1991-05-28

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE: To maximize the breakdown voltage, without compromising the series resistance of a power stage and reliability of the device by making the min. distance of a structure junction from an embedded drain region shorter than or equal to that of this region from the junction of the peripheral region. CONSTITUTION: In a possible embodiment for the terminal of a power stage, a min. distance d1 between an embedded drain region 6 and this insulation region 9 is made smaller than that d2 between the buried drain region 9 from a junction 10, lying between a substrate and drain. In creating a device region 15, a substrate-drain junction 10 of an MOS power transistor must be connected to the region 9, as described above. The terminal length given from the region 9 is equal to the sum of the side face diffusions of the insulation regions, its photo-masked opening and error layout allowance. Its structure can maximize the operating voltage, without changing the series resistance of the power stage.

公开(公告)号：DE69124289D1

公开(公告)日：1997-03-06

申请号：DE69124289

申请日：1991-05-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/772 ,  H01L29/06

Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.

公开(公告)号：IT1244239B

公开(公告)日：1994-07-08

申请号：IT661090

申请日：1990-05-31

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L

Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.

公开(公告)号：DE69520281T2

公开(公告)日：2001-08-09

申请号：DE69520281

申请日：1995-12-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONIO

IPC: H01L23/482 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69520281D1

公开(公告)日：2001-04-12

申请号：DE69520281

申请日：1995-12-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONIO

IPC: H01L23/482 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69124289T2

公开(公告)日：1997-06-19

申请号：DE69124289

申请日：1991-05-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/772 ,  H01L29/06

Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.

公开(公告)号：IT9006610A1

公开(公告)日：1991-12-01

申请号：IT661090

申请日：1990-05-31

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： GRIMALDI ANTONIO ,  ZAMBRANO RAFFAELE

IPC: H01L21/8249 ,  H01L20060101 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

公开(公告)号：JP2000357796A

公开(公告)日：2000-12-26

申请号：JP2000150927

申请日：2000-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI ANTONIO ,  GRIMALDI ANTONIO ,  FERLA GIUSEPPE

IPC: H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To resist the high operating voltage whereto a device is subjected, by providing a voltage divider wherein an edge termination includes a plurality of MOS transistors connected in series with each other, and by providing connectively the edge termination between the terminals of a power constituting element whose drivings are impossible. SOLUTION: A device 1 comprises a MOSFET power transistor 21 connected with an edge termination 100. The power transistor 21 is connected in parallel with the series circuit comprising a diode 41 plus the series circuit comprising PMOS parasitic transistors 31, 32, 33, 34. To allow the current flowing from a source terminal S4 of the fourth PMOS parasitic transistor 34 to a source S of the MOSFET power transistor 21, these PMOS parasitic transistors 31-34 are switched on respectively when their respective sources overcome the respective threshold voltages of the PMOS parasitic transistors 31-34. Therefore, there is obtained a limit to the high operating voltage whereto the device 1 is subjected.