公开(公告)号：WO2004112128A3

公开(公告)日：2005-07-14

申请号：PCT/US2004016347

申请日：2004-05-25

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing such mounted devices for stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供一种将集成电路器件安装到衬底上的系统和方法，以及用于使用这种安装的器件用于堆叠模块的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中所公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：WO2008051853A3

公开(公告)日：2009-05-07

申请号：PCT/US2007081964

申请日：2007-10-19

Applicant: STAKTEK GROUP LP ,  PARTRIDGE JULIAN ,  SZEWERENKO LELAND ,  WEHRLY JAMES DOUGLAS JR

Inventor： PARTRIDGE JULIAN ,  SZEWERENKO LELAND ,  WEHRLY JAMES DOUGLAS JR

IPC: H01L41/083

CPC classification number: H01L25/0657 ,  H01L23/5387 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/90 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/00

Abstract: A system and method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die (8) to a substrate (4) opposite a first die (6) bonded to the substrate (4). The second die (8) is bonded using heat conducted through the first die (6) to the substrate (4), and optionally through an underfill material. The first (6) and second (8) die are connected such that bumps (10) are connected to common bonding pads (12) on the substrate (4). Bumps (10) on one of the die extend through openings in the substrate (4) to connect to the common bonding pads (12). The bonding pads (12) are within the perimeter of the first die (6).

Abstract translation: 一种用于使用热压粘合或热超声键合来组装双模集成电路封装的系统和方法，用于将第二裸片（8）与与衬底（4）相对的第一裸片（6）相对的衬底（4）结合。 第二模具（8）使用通过第一模具（6）传导的热量与基板（4）结合，并且任选地通过底部填充材料粘结。 第一（6）和第二（8）管芯被连接成使得凸块（10）连接到衬底（4）上的公共接合焊盘（12）。 其中一个模具上的凸起（10）延伸穿过基板（4）中的开口，以连接到公共接合焊盘（12）。 接合焊盘（12）在第一管芯（6）的周边内。

公开(公告)号：WO2007053523A3

公开(公告)日：2007-10-04

申请号：PCT/US2006042232

申请日：2006-10-27

Applicant: STAKTEK GROUP LP ,  PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

Inventor： PARTRIDGE JULIAN ,  WEHRLY JAMES DOUGLAS ,  ROPER DAVID L ,  VILLANI JOSEPH

IPC: H01L23/52 ,  H01L25/065

CPC classification number: H01L23/49833 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H05K3/305 ,  H05K2201/056 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to add ional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.

Abstract translation: 本发明将集成电路封装堆叠到电路模块中。 在优选实施例中，分别将焊膏和主粘合剂施加到柔性电路上的选定位置。 补充粘合剂用于在柔性电路，CSP或其他组件上添加离子位置。 柔性电路和CSP彼此靠近。 在回流焊操作期间，施加力并且CSP朝柔性电路折叠，取代主粘合剂和辅助粘合剂。 补充粘合剂建立了为柔性电路提供额外支撑的粘合。 在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此粘合或粘合到其他组件。 快速粘合粘合剂在组装期间保持粘合的封装和/或部件的对齐，并且结构粘合粘合剂为粘合提供额外的强度和/或结构完整性。

公开(公告)号：WO2005114726A2

公开(公告)日：2005-12-01

申请号：PCT/US2005016764

申请日：2005-05-11

Applicant: STAKTEK GROUP LP ,  WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

Inventor： WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L23/3114 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/107

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以呈现一个或多个导电层，优选实施例具有两个导电层。 形式标准沿着下平面表面设置并横向延伸超过堆叠模块中的一个或多个CSP的包装。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，形式标准例如由导热材料例如铜构成。

公开(公告)号：WO2005010990A3

公开(公告)日：2005-05-06

申请号：PCT/US2004023152

申请日：2004-07-20

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/373 ,  H01L23/485

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded. The stacked modules make use of flexible substrates, low-profile contacts and form standarads for folding substrates.

Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，无论是CSP还是带引线。 堆叠的模块使用柔性基板，低轮廓接触和形成用于折叠基板的标准。

公开(公告)号：WO2005112100A3

公开(公告)日：2006-08-24

申请号：PCT/US2005013336

申请日：2005-04-19

Applicant: STAKTEK GROUP LP ,  PARTRIDGE JULIAN ,  WEHRLY JR DOUGLAS

Inventor： PARTRIDGE JULIAN ,  WEHRLY JR DOUGLAS

IPC: H01L23/02 ,  H01L21/44 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例中，与一个或多个CSP相关联的形式标准提供了一种物理形式，其允许在广泛的CSP包装系列中发现的许多变化的包装尺寸被利用，同时使用标准连接柔性 电路设计。 在优选实施例中，在CSP和形式标准的组合连接到柔性电路之前，下CSP的触点将被压缩，以在CSP和柔性电路之间形成下部轮廓接触。

公开(公告)号：EP1741134A4

公开(公告)日：2009-12-02

申请号：EP05737564

申请日：2005-04-19

Applicant: STAKTEK GROUP LP

Inventor： PARTRIDGE JULIAN ,  WEHRLY JR DOUGLAS

IPC: H01L23/02 ,  H01L21/44 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00